In April 1995, WINLAB (the Wireless Infonnation Network Lab­ oratory at Rutgers University) hosted the Fifth WINLAB Workshop on Third Generation Wireless Infonnation Networks. This workshop brings together a select group of experts interested in the future of Personal Communications, Mobile Computing and other services supported by wireless communications. As a sequel to Kluwer books on previous WINLAB workshops,l this volume assembles written versions of presentations of the Fifth Workshop. The last few years have been exciting for the field of wireless communications. The second generation systems that have absorbed our attention during those years are becoming commercial realities. Everyone is looking forward to PCS, especially in light of the recent auctions. We see an explosion of technical alternatives for meeting the demand for wireless communications. We also have applications in search of the best technologies rather than the reverse. The papers included provide new insights into many of the issues needing resolution for the successful introduction of the new services by the end of the decade. The authors represent views from both industry and universities from a number of nations. They are grouped into four main categories: Architecture, Radio Resource Management, Access, and Mobile Data, Mobile Networks.

Software Synthesis from Dataflow Graphs addresses the problem of generating efficient software implementations from applications specified as synchronous dataflow graphs for programmable digital signal processors (DSPs) used in embedded real- time systems. The advent of high-speed graphics workstations has made feasible the use of graphical block diagram programming environments by designers of signal processing systems. A particular subset of dataflow, called Synchronous Dataflow (SDF), has proven efficient for representing a wide class of unirate and multirate signal processing algorithms, and has been used as the basis for numerous DSP block diagram-based programming environments such as the Signal Processing Workstation from Cadence Design Systems, Inc., COSSAP from Synopsys® (both commercial tools), and the Ptolemy environment from the University of California at Berkeley.

Symbolic Boolean manipulation using binary decision diagrams (BDDs) has been successfully applied to a wide variety of tasks, particularly in very large scale integration (VLSI) computer-aided design (CAD). The concept of decision graphs as an abstract representation of Boolean functions dates back to the early work by Lee and Akers. In the last ten years, BDDs have found widespread use as a concrete data structure for symbolic Boolean manipulation. With BDDs, functions can be constructed, manipulated, and compared by simple and efficient graph algorithms. Since Boolean functions can represent not just digital circuit functions, but also such mathematical domains as sets and relations, a wide variety of CAD problems can be solved using BDDs.

Adaptive filtering is commonly used in many communication applications including speech and video predictive coding, mobile radio, ISDN subscriber loops, and multimedia systems. Existing adaptive filtering topologies are non-concurrent and cannot be pipelined. Pipelined Adaptive Digital Filters presents new pipelined topologies which are useful in reducing area and power and in increasing speed. If the adaptive filter portion of a system suffers from a power-speed-area bottleneck, a solution is provided.

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Provides a concise exposition of all major issues in clocking large microprocessors and SoCs
Contains information on clock generation and distribution, clocking elements, testability, alternative clocking styles, special techniques, and dealing with scaling and process variation
Includes in-depth coverage of topics by well-known experts in industry and academia

Introduction to the C++ Programming Language and the C++ Standard Library

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With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid “tra?c jams”; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ?ow congestion-aware. The book explores this tradeo? that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a circuit, while still ensuring that the circuit remains routable? It begins by motivating the c- gestion problem, explaining why this problem is important and how it will trend. It then progresses with comprehensive discussions of the techniques available for estimating and optimizing congestion at various stages in the design ?ow.

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A critical step in the design of a DSP system is to identify for each of its components (DSP kernels) an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. The book covers the entire solution space comprising both hardware multiplier-based and multiplex-less architectures that offer varying degrees of programmability. For each of the implementation styles, several algorithmic and architectural transformations are proposed so as to optimally implement weighted-sum based DSP kernels over the area-display-power space.