Field-programmable gate arrays (FPGAs), which are pre-fabricated, programmable digital integrated circuits (ICs), provide easy access to state-of-the-art integrated circuit process technology, and in doing so, democratize this technology of our time. This book is about comparing the qualities of FPGA – their speed performance, area and power consumption, against custom-fabricated ICs, and exploring ways of mitigating their de ciencies. This work began as a question that many have asked, and few had the resources to answer – how much worse is an FPGA compared to a custom-designed chip? As we dealt with that question, we found that it was far more dif cult to answer than we anticipated, but that the results were rich basic insights on fundamental understandings of FPGA architecture. It also encouraged us to nd ways to leverage those insights to seek ways to make FPGA technology better, which is what the second half of the book is about. While the question “How much worse is an FPGA than an ASIC?” has been a constant sub-theme of all research on FPGAs, it was posed most directly, some time around May 2004, by Professor Abbas El Gamal from Stanford University to us – he was working on a 3D FPGA, and was wondering if any real measurements had been made in this kind of comparison. Shortly thereafter we took it up and tried to answer in a serious way.

VHDL Answers to Frequently asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp. lang. vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error free, and simulation efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complete simulatable examples. This book is intended for those who are seeking an enhanced proficiency in VHDL. Its target audience includes: 1. Engineers. The book addresses a set of problems commonly experienced by real users of VHDL. It provides practical explanations to the questions, and suggests practical solutions to the raised issues. It also includes packages to achieve common utilities, useful in the generation of debug code aDd testbench designs. These packages include conversions to strings (the IMAGE package), generation of Linear Feedback Shift Registers (LFSR), Multiple Input Shift Register (MISR), and random number generators.

The Verilog hardware description language (HDL) provides the ability to describe digital and analog systems. This ability spans the range from descriptions that express conceptual and architectural design to detailed descriptions of implementations in gates and transistors. Verilog was developed originally at Gateway Design Automation Corporation during the mid-eighties. Tools to verify designs expressed in Verilog were implemented at the same time and marketed. Now Verilog is an open standard of IEEE with the number 1364. Verilog HDL is now used universally for digital designs in ASIC, FPGA, microprocessor, DSP and many other kinds of design-centers and is supported by most of the EDA companies. The research and education that is conducted in many universities is also using Verilog. This book introduces the Verilog hardware description language and describes it in a comprehensive manner. Verilog HDL was originally developed and specified with the intent of use with a simulator. Semantics of the language had not been fully described until now. In this book, each feature of the language is described using semantic introduction, syntax and examples. Chapter 4 leads to the full semantics of the language by providing definitions of terms, and explaining data structures and algorithms. The book is written with the approach that Verilog is not only a simulation or synthesis language, or a formal method of describing design, but a complete language addressing all of these aspects. This book covers many aspects of Verilog HDL that are essential parts of any design process.

Beginning in the mid 1980's, VLSI technology had begun to advance in two directions. Pushing the limit of integration, ULSI (Ultra Large Scale Integration) represents the frontier of the semiconductor processing technology in the campaign to conquer the submicron realm. The application of ULSI, however, is at present largely confined in the area of memory designs, and as such, its impact on traditional, microprocessor-based system design is modest. If advancement in this direction is merely a natural extrapolation from the previous integration generations, then the rise of ASIC (Application-Specific Integrated Circuit) is an unequivocal signal that a directional change in the discipline of system design is in effect. In contrast to ULSI, ASIC employs only well proven technology, and hence is usually at least one generation behind the most advanced processing technology. In spite of this apparent disadvantage, ASIC has become the mainstream of VLSI design and the technology base of numerous entrepreneurial opportunities ranging from PC clones to supercomputers. Unlike ULSI whose complexity can be hidden inside a memory chip or a standard component and thus can be accommodated by traditional system design methods, ASIC requires system designers to master a much larger body of knowledge spanning from processing technology and circuit techniques to architecture principles and algorithm characteristics. Integrating knowledge in these various areas has become the precondition for integrating devices and functions into an ASIC chip in a market-oriented environment. But knowledge is of two kinds.

The developments in mesh generation are usually driven by the needs of new applications and/or novel algorithms. The last decade has seen a renewed interest in mesh generation and adaptation by the computational engineering community, due to the challenges introduced by complex industrial problems.
Another common challenge is the need to handle complex geometries. Nowadays, it is becoming obvious that geometry should be persistent throughout the whole simulation process. Several methodologies that can carry the geometric information throughout the simulation stage are available, but due to the novelty of these methods, the generation of suitable meshes for these techniques is still the main obstacle for the industrial uptake of this technology.

General Applications of BEM to electromagnetic problems are comparatively new although the method is ideally suited to solve these problems, which usually involve unbounded domains. The present volume comprises contributions by eminent researchers working on applications of boundary elements in electromagnetic problems. The volume deals with the solutions of Maxwell's equation for three-dimensional as well as two-dimensional cases. It also discusses combination of BEM with FEM particularly in the case of saturated media. Some chapters specifically deal with the design of electromagnetic devices. The book is essential reading to those engineers and scientists, who are interested in the state of the art for electrical and electromagnetic application of boundary elements. It is also an important reference for those engineers who are working on the design of electromagnetic components many of which can be advantageously carried out using BEM.

The assembly of electronic circuit boards has emerged as one of the most significant growth areas for robotics and automated assembly. This comprehensive volume, which is an edited collection of material mostly published in "Assembly Engineering" and "Electronic Packaging and Production", will provide an essential reference for engineers working in this field, including material on Multi Layer Boards, Chip-on-board and numerous case studies. Frank J. Riley is senior vice-president of the Bodine Corporation and a world authority on assembly automation.

The publication of Introduction to Robotics is one among the results of many years' work by the authors of this book in the study of robotics. During the first stage of this work, devoted to locomotion robots and anthropomorphic mechanisms in particular, a number of papers were published in the period 1974-76. The most prominent of them is M. VukobratoviC's Legged Locomotion Systems and Anthropomorphic Mechanisms, published in English, Russian, Japanese and Chinese.

In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its “unrealistic optimism,” Moore’s prediction has remained valid for far longer than even he imagined: today, chips built using state– the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore’s law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a ?rst-order functional language designedspeci?callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di?erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits.

In this book, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism.

VHDL Coding Styles and Methodologies, Edition is a follow up book to the first edition of same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy to read book that gave in depth coverage of both, the language and coding methodologies. This edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD. The CD also includes the GNU toolsuite with EMACS language sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included a timed evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity included a timed version of Synplify, a very efficient, user friendly and easy to use FPGA synthesis tool. Synplify provides a user both the RTL and gate level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool.

See How the Magic Happens

Fully-depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V. The topics include the minimum required knowledge of the fabrication of SOI substrates; FD-SOI devices and the latest developments in device and process technologies; and ultralow-voltage circuits, such as digital circuits, analog/RF circuits, and DC-DC converters. Each ultra-low-power technique related to devices and circuits is fully explained using figures to help understanding.