Vsd - Pipelining Risc-V With Transaction-Level Verilog

Front end VLSI design can’t get easier than this

What you'll learn
Students will be able to use and implement concepts of pipelining using TL-verilog language and Makerchip platform
Build their own verilog models for IP's using a simpler and powerful Verilog design environment
Requirements
You should know basics of digital design like flip-flops, gates, clock, etc.
You should have finished RISC-V ISA - Part 1a course on Udemy if new to CPU microarchitecture
You should have a modern web browser like chrome, and login to Makerchip to ensure compatibility
Description
Do you want to build just verilog models or high-quality verilog models in half the time? 
Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser?


How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”. I encourage and welcome you to think in the right direction with experts from this field in my webinar on “Pipelining RISC-V with Transaction-Level Verilog” which was conducted on 10th Feb’ 2018 with Steve Hoover, Founder of Redwood EDA and Makerchip Platform
This webinar is really important for people
who have taken up my RISC-V ISA course on Udemy, as we will show
efficient RTL implementation of some instructions in this
one.



Enjoy the webinar and Happy Learning….

Overview

Section 1: Introduction

Lecture 1 Introduction and welcome to participants and Steve

Lecture 2 Launch of makerchip.com and introduction to webinar motive

Lecture 3 Live QnA with participants on webinar content and motive

Section 2: RISC-V overview and instruction Pipelining Concepts

Lecture 4 Pipelined RISC-V block diagram description

Lecture 5 RISC-V waterfall diagram and hazards

Lecture 6 Live QnA with participants regarding processor architecture

Section 3: IP design methodology

Lecture 7 RISC-V IP challenges and WARP-V development progress

Lecture 8 Why Transaction-Level verilog?

Lecture 9 Introduction to makerchip.com platform

Section 4: Examples using makerchip.com platform

Lecture 10 More about makerchip.com and first exercise for participants

Lecture 11 Inverter exercise for participants and LIVE QnA about makerchip.com platform

Lecture 12 Sequential logic - Fibonacci series example

Lecture 13 LIVE QnA with participants regarding exercises

Section 5: Pipelines

Lecture 14 Pythagoras theorem example of pipeline

Lecture 15 Retiming implementation in TL-Verilog vs system verilog

Lecture 16 Fibonnaci series pipeline and concept of validity

Lecture 17 Exercise to identify error conditions in WARP-V

Section 6: Pipeline Interactions

Lecture 18 WARP-V operand mux

Lecture 19 Register bypass and time division multiplexing (TDM) example

Lecture 20 Solve TDM exercise - Part1

Lecture 21 Solve TDM exercise - Part2

Lecture 22 LIVE QnA with participants regarding pipeline interactions and other topics

Section 7: Miscellaneous Topics

Lecture 23 Hierarchy and interfaces in TL-Verilog

Lecture 24 LIVE QnA with participants on WARP-V core

Lecture 25 Transaction flow and wrap-up course content

Section 8: Certification challenge and conclusion

Lecture 26 Certification challenge problem statement

Lecture 27 Conclusion

Anyone who wants to learn transaction-level verilog,Anyone who wants to stay ahead of curve in frontend VLSI,Anyone who wants to learn and implement pipelining concepts in field of computer architecture