Verilog For An Fpga Engineer With Xilinx Vivado Design Suite

Using Xilinx FPGA's

What you'll learn

Fundamentals of Verilog Programming that will help to ace RTL Engineer Job Interviews.

Understand Vivado Design Suite flow for Digital System Design.

Hardware Debugging in Vivado viz. Integrated Logic Analyzer, Virtual I/O.

Different Modelling Styles in Hardware Description Language.

How to use Xilinx IP's and create Custom IP's.

IP integrator Design flow of the Vivado.

Writing Verilog Test benches.

Design of some real world projects such as : PMOD DA4 DAC interface, Function Generator, Small Processor Architecture, UART Interface, PWM, BIST for Development boards and many more.

Common Interview Questions

Requirements

Fundamental of Digital Circuit will give an added advantages.

Description

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the Verilog language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain.  Most of the concepts are explained considering practical real examples to help to build logic. The course illustrates the usage of  Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

Overview

Section 1: Installing Vivado

Lecture 1 Target

Lecture 2 How to download and Install Vivado IDE on PC

Lecture 3 Adding License File

Lecture 4 Xilinx Vivado Webpack LIC FILE

Lecture 5 Adding boards such as Nexys 4 DDR which are not available in the Vivado

Lecture 6 Board Files

Lecture 7 Common Error with Vivado: Incorrect Microsoft Visual C++ redistributable package

Lecture 8 Cloud based IDE for learning Verilog constructs without Vivado

Section 2: Vivado Design Flow Part 1

Lecture 9 Target

Lecture 10 Creating New Project and adding Source File

Lecture 11 Adding Source Code

Lecture 12 Understanding Source Code

Lecture 13 RTL Schematic P1

Lecture 14 RTL Schematic P2

Lecture 15 Behavioral Simulation : Force Constant

Lecture 16 Behavioral Simulation : Force Clock

Lecture 17 Typical Testbench

Lecture 18 Synthesis P1

Lecture 19 Synthesis P2

Lecture 20 Implementation

Lecture 21 Generating Programming File

Lecture 22 Vivado GUI Insight

Lecture 23 Code for next Video

Lecture 24 Useful Simulation Options

Lecture 25 Simulation Multibit ports P1

Lecture 26 Simulation Multibit ports P2

Lecture 27 Use of RTL View in Vivado

Lecture 28 Use of Post Synthesis View in Vivado

Section 3: Vivado Design Flow Part 2

Lecture 29 Target

Lecture 30 Project Types in Vivado

Lecture 31 Understanding I/O Planning Project

Lecture 32 Types of Project and their meaning in Vivado

Lecture 33 Understanding Synthesis Settings

Lecture 34 Clock Gating in Synthesis

Lecture 35 FSM Encoding

Lecture 36 Fundamentals of FSM Encoding

Lecture 37 Vivado Pre-configured Synthesis Strategies

Lecture 38 Implementation Strategies Demonstration in Vivado

Lecture 39 Code

Lecture 40 FPGA Design Flow

Lecture 41 References for further study

Lecture 42 Complete FPGA Design Flow Demonstration

Lecture 43 Code Used in the Demonstration

Lecture 44 Incorrect Sim waveform in Post Synthesis and Post Implementation Testbench

Lecture 45 Understanding Folder hierarchy of Vivado

Section 4: Commonly Asked Question's from previous Module

Lecture 46 Q1

Lecture 47 Q2

Section 5: Fundamentals of Verilog

Lecture 48 Target

Lecture 49 Identifiers

Lecture 50 Getting Started with reg and wire type

Lecture 51 Number Format

Lecture 52 Verilog Datatypes

Lecture 53 Reporting Mechanism P1

Lecture 54 Reporting Mechanism P2

Lecture 55 Demonstration Reporting Mechanism P1

Lecture 56 Demonstration Reporting Mechanism P2

Lecture 57 Code

Lecture 58 Datatypes Demonstration

Lecture 59 Code

Lecture 60 Verilog Operators P1

Lecture 61 Verilog Operators P2

Lecture 62 Verilog Operators P3

Lecture 63 Verilog Operators P4

Lecture 64 Code

Section 6: Commonly Asked Question's from previous Module

Lecture 65 Q1

Lecture 66 Q2

Lecture 67 Q3

Lecture 68 Q4

Lecture 69 Q5

Lecture 70 Q6

Lecture 71 Q7

Section 7: Modeling Styles

Lecture 72 Target

Lecture 73 Modeling Style P1

Lecture 74 Modeling Style P2

Lecture 75 Demonstration

Section 8: Assignment Operators in Verilog

Lecture 76 Target

Lecture 77 Procedural Assingment Vs Continuous Assingment

Lecture 78 Understanding Continuous Assignment

Lecture 79 Code

Lecture 80 Understanding Procedural Assignment Operator

Lecture 81 Code

Lecture 82 Differences in Continuous and Procedural Assignment Operators

Lecture 83 Demonstration

Lecture 84 Code

Lecture 85 Swapping of Variable values

Lecture 86 Code

Section 9: FAQ

Lecture 87 What happens if I declare blocking statements rather than NB in Sequential Ckt

Section 10: Behavioral Modeling Style

Lecture 88 Target

Lecture 89 Behavioral Modeling Skeleton

Lecture 90 Initial Block : Behavioral Modeling Constructs P1

Lecture 91 Always Block : Behavioral Modeling Constructs P2

Lecture 92 Blocking and Non-Blocking Assig. Operator : Behavioral Modeling Construct P3

Lecture 93 Demonstration

Lecture 94 Code

Lecture 95 IF ELSE skeleton

Lecture 96 2:1 Mux : Combinational Circuit P1

Lecture 97 Code

Lecture 98 4:1 Mux : Combinational Circuit P2

Lecture 99 Code

Lecture 100 Case Skeleton

Lecture 101 Binary to 7-Seg Converter

Lecture 102 Code

Lecture 103 Differences between IF ELSE and CASE

Lecture 104 Code

Lecture 105 Data Flipflop : Sequential Circuit P1

Lecture 106 D-Flipflop Code

Lecture 107 Up Counter : Sequential Circuit P2

Lecture 108 Counter Code

Lecture 109 Special Counter P1

Lecture 110 Special Counter P2

Section 11: Commonly Asked Question's from previous Module

Lecture 111 Q1

Lecture 112 Q2

Lecture 113 Q3

Section 12: Gate Level Modeling Style

Lecture 114 Target

Lecture 115 Half-adder : All nets defined

Lecture 116 Code

Lecture 117 Full-adder : Few Undefined nets

Lecture 118 Alternative Method

Section 13: Switch level Modeling Style

Lecture 119 Target

Lecture 120 Fundamentals

Lecture 121 Inverter

Lecture 122 Code

Lecture 123 NAND GATE

Lecture 124 Code

Lecture 125 AND Gate

Lecture 126 Code

Section 14: Structural Modeling Style

Lecture 127 Target

Lecture 128 Fundamentals P1

Lecture 129 Fundamentals P2

Lecture 130 Full adder

Lecture 131 Code

Lecture 132 4:1 Mux

Lecture 133 Code

Section 15: Schematic based Design Entry with IP integrator and Xilinx IP's

Lecture 134 Target

Lecture 135 How to create IP

Lecture 136 Create a BD with IP

Lecture 137 How to refresh IP repository

Lecture 138 How to Update IP Source Code

Lecture 139 Override GUI parameters

Lecture 140 Implementing 4-bit Shift Register

Lecture 141 Implementing 4-bit Ripple Carry Adder P1

Lecture 142 Implementing 4-bit Ripple Carry Adder P2

Lecture 143 Design of Digital Filters using IP integrator

Section 16: Memories

Lecture 144 Target

Lecture 145 Memory Fundamentals

Lecture 146 Understanding Memory Size

Lecture 147 Single Port RAM : GENERAL METHOD

Lecture 148 Code

Lecture 149 Single Port RAM : LANGUAGE TEMPLATE

Lecture 150 Single Port RAM : IP Method

Lecture 151 Single Port ROM

Lecture 152 Matlab Code

Lecture 153 COE File

Section 17: Commonly Asked Question's from previous Module

Lecture 154 Q1

Section 18: Finite State Machines

Lecture 155 Target

Lecture 156 FSM Fundamentals

Lecture 157 Moore FSM

Lecture 158 Mealy FSM

Lecture 159 FSM Implementation Methodology

Lecture 160 3-Process Methodology : Moore FSM

Lecture 161 Code

Lecture 162 2-Process Methodology : Moore FSM

Lecture 163 Code

Lecture 164 1-Process Methodology : Moore FSM

Lecture 165 Code

Lecture 166 3-Process Methodology : Mealy FSM

Lecture 167 2-Process Methodology : Mealy FSM

Lecture 168 Code

Lecture 169 1-Process Methodology : Mealy FSM

Lecture 170 Code

Lecture 171 Recommended Methodologies for FSM

Lecture 172 Synchronus Vs Asynchronus System

Lecture 173 Sequence Detector

Lecture 174 Overlapping Sequence Detector

Lecture 175 Non-Overlapping Sequence Detector

Lecture 176 Overlapping Sequence Detector

Lecture 177 Code

Lecture 178 Non-Overlapping Sequence Detector

Lecture 179 Code

Section 19: Commonly Asked Question's from previous Module

Lecture 180 Q1 ( Sourav Biswal )

Lecture 181 Q2 (Yashwant Kumar)

Lecture 182 Q3 (Apoorva Srivastava)

Section 20: Writing Testbenches

Lecture 183 Target

Lecture 184 Understanding Signals

Lecture 185 Generating Fixed Point Clock Period

Lecture 186 Generating Floating Point Clock Signals

Lecture 187 Demonstration

Lecture 188 Code

Lecture 189 Generating Reset Signal

Lecture 190 Generating Stimulus for Multibit Signals

Lecture 191 Understanding Task

Lecture 192 2:1 Mux

Lecture 193 Code

Lecture 194 Binary to Excess-3 Converter

Lecture 195 Code

Lecture 196 Data Flipflop

Lecture 197 Code

Lecture 198 Counter

Lecture 199 Code

Lecture 200 Single Port RAM

Lecture 201 Code

Section 21: Hardware Debugging with Vivado (Required Hardware)

Lecture 202 Target

Lecture 203 Integrated Logic Analyzer P1

Lecture 204 Integrated Logic Analyzer P2

Lecture 205 Integrated Logic Analyzer P3

Lecture 206 ILA with IP Integrator

Lecture 207 Virtual I/O (VIO) P1

Lecture 208 Virtual I/O (VIO) P2

Lecture 209 Virtual I/O (VIO) P3

Section 22: File I/O

Lecture 210 Target

Lecture 211 Accessing File

Lecture 212 Writing Data to File

Lecture 213 Code

Lecture 214 Reading Data from File

Lecture 215 Reading Multiple Columns from File

Lecture 216 Code

Lecture 217 Exampl 1 : Adder

Lecture 218 Code

Lecture 219 Example 2: RAM

Lecture 220 Code

Section 23: Projects

Lecture 221 Target

Lecture 222 Understanding UART Protocol

Lecture 223 Clock for desired Baud

Lecture 224 UART Transmitter

Lecture 225 UART Receiver

Lecture 226 UART TB

Lecture 227 Design Code

Lecture 228 TB Code

Lecture 229 Serial Peripheral Interface

Lecture 230 Code

Lecture 231 PWM

Lecture 232 Code

Lecture 233 LCD

Lecture 234 Code

Lecture 235 BIST for SW and LED

Lecture 236 Code

Lecture 237 I2C

Lecture 238 Code

Section 24: RTL for Synthesis

Lecture 239 Good Practices

Section 25: FPGA Architecture Fundamentals

Lecture 240 Target

Lecture 241 Need of Reprogrammable architecture

Lecture 242 PLD Classification

Lecture 243 Simulating Programmable Logic

Lecture 244 PROM Demonstration on NI Multisim IDE

Lecture 245 PAL and PLA

Lecture 246 SPLD and GAL

Lecture 247 Going through GAL datasheet : 16V8

Lecture 248 SPLD and GAL Summary

Lecture 249 Understanding CPLD architecture

Lecture 250 Introduction to FPGA Architecture

Lecture 251 Wide Multiplexer Usage

Lecture 252 Understanding Spartan 6 Architecture

Lecture 253 Spartan 6 FPGA Architecture Summary

Section 26: Commonly Asked Question's from previous Module

Lecture 254 How 6-input LUT implements 4:1 Mux ? (Amaresh Mandal)

Section 27: Interview Preparations

Lecture 255 Resume Format

Lecture 256 Common Interview Questions

Section 28: Next Step

Lecture 257 RTL Verification with SystemVerilog for Newbie

Lecture 258 RTL Verification with UVM for Newbie

VLSI Job Seeker/ Graduate student looking to pursue career as RTL Engineer/ Design Engineer/ Verification Engineer.,Anyone interested to learn Xilinx FPGA/ Vivado Design Suite/ Verilog Hardware Description Language,Anyone interested to start career in ASIC/ VLSI domain.