VSD - Signal Integrity
VSD - Signal Integrity
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 406 MB | Duration: 6h 34m
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 406 MB | Duration: 6h 34m
VLSI - Real and practical steps to build chip with minimum Signal Integrity issues!!
What you'll learn
To Learn Chip Design with minimal Crosstalk in the circuits.
To Design a Chip with minimal errors.
Requirements
Basic of VLSI and Chip Design
Description
Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.
Crosstalk is the interference caused due to communication between the circuits
Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.
Course Details
•Reasons for Crosstalk
•Introduction to Noise Margin
•Crosstalk Glitch Example
•Factors Affecting Glitch Height
•AC Noise Margin
•Timing Window Concepts
•Impact of Crosstalk on Setup and Hold Timing
•Techniques to reduce Crosstalk
•Power Supply Noise
Who this course is for
VLSI Engineers keen to Learn Backend of Chip Design
Physical Design Engineer
Students Learning VLSI Engineering