Step By Step Vhdl Programming For Xilinx Fpga & Cpld

Learn VHDL Programming for Xilinx FPGA Architecture & PCB Design : Skills suitable for Electronics Engineering Students

What you'll learn
VHDL Programming Synthesis & Simulation Xilinx FPGA & CPLD Devices Xilinx ISE Design Suite & Implementation
Requirements
Digitial Logic Design Concepts Basic knowledge of any Programming Language ( Like Ex. C Programming )
Description
Hello Dear Student ,Welcome for Learning  a Beginners Course with Basic Level Content focused on VHDL Programming as a beginner's reference , suitable for Electronics Polytechnic , Engineering & University Students & Hobbyists .Apart from VHDL Programming content  using Xilinx ISE Webpack Software , added the Content of  PCB Design at a Very Basic Level ( Only Single Layer PCB Design ) using EasyEDA Software . You may treat PCB Design Content as a complementary Content , if you are a Electronics Student . If you are interested  in only VHDL Programming , you may skip / ignore the Content of PCB Design .All the Content of this Course are based on Free Softwares & either On-Line Or Opensource Downloadable Softwares for Design / Programming .1. VHDL Programming using Xilinx ISE Webpack , a Free Downloadable Software ( After Creating your Account  / Registering on Xilinx Website ) .VHDL Programming Examples on Combinational & Sequential Digital Logic have been explained with Step by Step Approach i.e. VHDL Program , VHDL Test Bench , Synthesis & Behavioral Simulation ) . Also Programming Examples on VHDL based FSMs - Finite State Machines have been explained  .2. PCB Design Basics ( Only 1 - Layer PCB Design Examples ) using a OnLine & Free PCB Design Software “EasyEDA” ,( After Creating your Account / Registering on easyeda Website  .Single Layer PCB Design Examples have been Explained with Schematic Design , PCB Layout Design ( Component Placement ) & Track Routing using Single Layer Design.PCB Design Examples based on Through Hole Components & SMT ( Surface Mount ) Components have been explained .At the beginning , the Course Title was “ Step by Step VHDL Programming for Xilinx CPLD & FPGA ” , a Course in VHDL Programming for Beginner Level .My approach is to continuously add & update the Content of this Course , so-that it may be helpful specifically to Electronics Polytechnic , Engineering , University Students & also to Hobbyists .Course Update 2nd : ( Feb. 2021 ) : Added Content :  PCB Design Basics ( 1 Layer PCB  Design ) using EasyEDA software  .Course Update 1st : ( Octo. 2021 ) : Added Content : FSM Examples with VHDL Programming .Course Published ( In Sept. 2020 ) : Content of VHDL Programming using Xilinx ISE Webpack software .–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––-Instructor has more than a 22 Years of Design / Training Experience after M.Tech. ( Master of Technology ) in Electronics Design & Technology , which includes the Experience in Electronic Circuit Design , Embedded System ,  VLSI -  VHDL & Verilog Programming for Xilinx FPGAs , CPLDs using Xilinx ISE Tool / Xilinx Vivado Tool , PSOC1 using Cypress PSOC Designer & PSOC3 /PSOC4 using Cypress PSOC Creator , Microcontroller Programming  STM32 ( 32 Bit ARM Core Based ) using STM32cubeIDE , MCS-51 (8051 ) family using Keil uVision 4 , Programming ATMega 16/32/128 using Atmel AVR Studio , Programming Microchip PIC 16/18 using MPLAB , Arduino Programming for Arduino Uno , MSP430 of Texas Instruments with Energia , Raspberry Pi  & Raspbian Linux , Python Programming with Python 3.9 ( IDLE) , Python Thonny , Python Pycharm , Anaconda Navigator - Jupyter Notebook , Spyder Python , Google Colab , Crouzet Millenium 3 for PLC Programming  & also PCB design which includes PCB Softwares such as EasyEDA  , Eagle ( Fusion 360 ) , KiCad 5.1 , Fritzing & Express PCB . –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––-

Overview

Section 1: About IC Technology

Lecture 1 IC Technology - Introduction to ASIC , FPGA & EDA Tools

Section 2: FPGA Architecture

Lecture 2 Xilinx FPGA SPARTAN 6 Architecture

Section 3: VHDL Language Basics

Lecture 3 VHDL Basics

Section 4: VHDL(CPLD)-Design Entry,Synthesis & Verification - Basic Digital Logic

Lecture 4 VHDL - Basic Digital Logic ( Part 1 )

Lecture 5 Synthesis & Simulation ( Presentation )

Lecture 6 Synthesis & Behavioral Simulation - Basic Digital Logic ( Part 1 )

Lecture 7 VHDL - Basic Digital Logic ( Part 2 )

Lecture 8 Synthesis & Behavioral Simulation - Basic Digital Logic ( Part 2 )

Lecture 9 VHDL - Basic Digital Logic ( Part 3 )

Lecture 10 Synthesis & Behavioral Simulation - Basic Digital Logic ( Part 3 )

Lecture 11 VHDL - Basic Digital Logic ( Part 4 )

Lecture 12 Synthesis & Behavioral Simulation - Basic Digital Logic ( Part 4 )

Section 5: Applying Constraints to CPLD Design

Lecture 13 Applying Constraints to VHDL Design ( Pin Locking )

Section 6: Design Implementation - CPLD ( Xilinx )

Lecture 14 Fitter Report for CPLD

Section 7: Fast Track Learning: Entire Section 4 (All Logics)

Lecture 15 Fast Track : VHDL ( All Logics - Section 4 )

Lecture 16 Fast Track : Synthesis ( Section 4 - All Logics )

Lecture 17 Fast Track : Behavioral Simulation ( All Logics - Section 4 )

Section 8: VHDL Design ,Test Bench ,Synthesis & Verification - Basic Digital Logic ( FPGA )

Lecture 18 VHDL - Case Statement ( Presentation )

Lecture 19 VHDL Code - MUX ( 2:1 Multiplexer )

Lecture 20 Synthesis Process

Lecture 21 VHDL Test Bench

Lecture 22 Behavioral Simulation using Xilinx ISim Simulator

Section 9: Applying Constraints to FPGA Design

Lecture 23 Constraints Editing - Pin Locking

Section 10: (FPGA) VHDL Design ,TestBench,Synthesis & Verification - Combinational Logics

Lecture 24 VHDL Code - MUX ( 4:1 Multiplexer )

Lecture 25 VHDL Test Bench - 4:1 MUX

Lecture 26 Synthesis : 4:1 MUX

Lecture 27 Behavioral Simulation : 4 : 1 MUX

Lecture 28 VHDL - Decoder

Lecture 29 VHDL Test Bench - Decoder

Lecture 30 Synthesis - Decoder

Lecture 31 Behavioral Simulation - Decoder

Lecture 32 VHDL - Encoder

Lecture 33 VHDL Test Bench - Encoder

Lecture 34 Synthesis & Behavioral Simulation - Encoder

Lecture 35 Modified VHDL Code - Encoder

Lecture 36 VHDL - D Latch

Section 11: Fast Track Learning : Sections 8 & 10 ( Using when-else construct )

Lecture 37 Fast Track : VHDL ( Combinational Logic - using when else )

Lecture 38 Synthesis : Combinational Logics

Lecture 39 Fast Track : Test Bench ( Combinational Logics)

Lecture 40 Behavioral Simulation - Combinational Logics

Section 12: Arithmetic Digital Blocks -VHDLCode ,TestBench , Synthesis & Verification

Lecture 41 VHDL - Half Adder

Lecture 42 VHDL Test Bench - Half Adder

Lecture 43 Synthesis & Behavioral Simulation - Half Adder

Lecture 44 VHDL - Full Adder

Lecture 45 Test Bench - Full Adder

Lecture 46 Synthesis - Full Adder

Lecture 47 Behavioral Simulation - Full Adder

Section 13: VHDL Modeling Style - Behavioral Modeling

Lecture 48 VHDL Behavioral Modeling - 4 Bit Comparator

Lecture 49 Test Bench - 4 Bit Comparator ( Behavioral Modeling )

Lecture 50 Synthesis & Behavioral Simulation - 4 Bit Comparator ( Behavioral Modeling )

Section 14: VHDL Modeling Style - DataFlow Modeling

Lecture 51 VHDL DataFlow Modeling - 4 Bit Comparator

Lecture 52 VHDL Test Bench - 4 Bit Comparator ( Data Flow Modeling )

Lecture 53 Synthesis & Behavioral Simulation - 4 Bit Comparator ( Data Flow Modeling )

Section 15: VHDL Modeling Style - Structural Modeling

Lecture 54 VHDL - Structural Modeling ( 4 Bit Comparator )

Lecture 55 VHDL Test Bench - 4 Bit Comparator ( Structural Modeling )

Lecture 56 Synthesis & Behavioral Simulation - 4 Bit Comparator ( Structural Modeling )

Section 16: Sequential Logic Blocks - VHDL Code , TestBench,Synthesis & Verification (FPGA)

Lecture 57 VHDL - D FlipFlop

Lecture 58 VHDL Test Bench - D Flipflop

Lecture 59 Synthesis & Behavioral Simulation - D Flipflop

Lecture 60 VHDL - D FlipFlop With Asynchronous Reset

Lecture 61 VHDL - D FlipFlop With Synchronous Reset

Section 17: VHDL - Synchronous Logic Design - Part 1 ( Up Counter & Down Counter Design )

Lecture 62 VHDL - Binary Up Counter

Lecture 63 Test Bench - Binary Up Counter

Lecture 64 Synthesis & Behavioral Simulation - Binary Up Counter

Lecture 65 VHDL - Binary Down Counter with Test Bench , Synthesis & Simulation

Section 18: VHDL - Synchronous Logic Design - Part 2 ( Binary Up-Down Counter Designs )

Lecture 66 VHDL - 4 Bit Binary Up-Down Counter ( Synchronous )

Lecture 67 Synthesis - 4 bit Binary Up-Down counter ( Synchronous )

Lecture 68 VHDL Test Bench - Binary Up-Down Counter

Lecture 69 Behavioral Simulation- Binary Up-Down Counter ( 4 Bit - Synchronous )

Section 19: VHDL - Synchronous Logic Design - Part 3 ( Improved Binary Up - Down Counter )

Lecture 70 VHDL - Improved Binary Up-Down Counter ( 4 bit - Synchronous )

Lecture 71 Synthesis - Improved Binary Up-Down Counter

Lecture 72 Behavioral Simulation - Improved Binary Up-Down Counter

Section 20: Applying Pin Locking Constraints

Lecture 73 Physical Constraints - Pin Locking Constraints

Section 21: Applying Timing Constraints

Lecture 74 Timing Constraints - 4 Bit Binary Up-Down Counter

Section 22: Design Implementation - Xilinx FPGA

Lecture 75 Post Route Timing Simulation( Static Timing )

Section 23: VHDL - Synchronous Logic Design - Part 4 ( Gray Up-Down Counter Design )

Lecture 76 VHDL - Gray Up-Down Counter

Lecture 77 Synthesis : Gray Up-Down Counter

Lecture 78 Test Bench - Gray Up-Down Counter

Lecture 79 Behavioral Simulation - Gray Up-Down Counter

Section 24: VHDL - Synchronous Logic Design - Part 5 ( SISO Shift Register ) ( Xilinx FPGA )

Lecture 80 VHDL - Serial In Serial Out Shift Register ( SISO )

Lecture 81 Synthesis - SISO Shift Register

Lecture 82 VHDL Test Bench - SISO Shift Register

Lecture 83 Behavioral Simulation - SISO Shift Register

Section 25: VHDL - Synchronous Logic Design - Part 6 ( SIPO Shift Register ) ( Xilinx FPGA)

Lecture 84 VHDL - Serial In Parallel Out Shift Register ( SIPO )

Lecture 85 Synthesis - SIPO Shift Register

Lecture 86 VHDL Test Bench - SIPO Shift Register

Lecture 87 Behavioral Simulation - SIPO Shift Register

Section 26: VHDL - Synchronous Logic Design - Part 7 ( PISO Shift Register ) ( Xilinx FPGA )

Lecture 88 VHDL - Parallel In Serial Out Shift Register

Lecture 89 Synthesis - PISO Shift Register

Lecture 90 VHDL Test Bench - PISO Shift Register

Lecture 91 Behavioral Simulation - PISO Shift Register

Section 27: VHDL - Synchronous Logic Design - Part 8 ( PIPO Shift Register ) ( Xilinx FPGA )

Lecture 92 VHDL - Parallel In Parallel Out Shift Register

Lecture 93 Synthesis - PIPO Shift Register

Lecture 94 VHDL Test Bench - PIPO Shift Register

Lecture 95 Behavioral Simulation - PIPO Shift Register

Section 28: About State Machine Design - FSMs : Sequence Detector Implementtion

Lecture 96 State Machine Design- Moore FSM & Mealy FSM for Sequence Detector :

Section 29: VHDL State Machine Design - Moore FSM for Sequence Detector

Lecture 97 Moore FSM VHDL Design : Sequence Detector Example

Lecture 98 Synthesis : Moore FSM : Sequence Detector

Lecture 99 Test Bench : Moore FSM : Sequence Detector

Lecture 100 Simulation : Moore FSM : Sequence Detector

Section 30: VHDL State Machine Design - Mealy FSM for Sequence Detector

Lecture 101 VHDL : Mealy FSM Example : Sequence Detector

Lecture 102 Synthesis : Mealy FSM Example : Sequence Detector

Lecture 103 Test Bench : Mealy FSM Example : Sequence Detector

Lecture 104 Simulation : Mealy FSM Example : Sequence Detector

Section 31: About State Machine Design - FSMs : Binary Up/Down Counter Implementation

Lecture 105 State Machine Designs for Counters

Section 32: Moore State Machine ( FSM ) Design : Binary Up/Down Counter

Lecture 106 VHDL - Moore FSM : Binary Up/Down Counter Design

Lecture 107 Synthesis - Moore FSM : Binary Up/Down Counter

Lecture 108 Test Bench - Moore FSM : Binary Up/Down Counter

Lecture 109 Simulation - Moore FSM : Binary Up/Down Counter

Lecture 110 Changing from Enumerated to Integer Data Type

Section 33: Mealy State Machine ( FSM ) Design : Binary Up/Down Counter

Lecture 111 VHDL : Mealy FSM : Binary Up/Down Counter Design

Lecture 112 Synthesis : Mealy FSM : Binary Up/Down Counter

Lecture 113 Test Bench : Mealy FSM : Binary Up/Down Counter

Lecture 114 Simulation : Mealy FSM : Binary Up/Down Counter

Section 34: FSM - Finite State Machine for Gray Up/Down Counter

Lecture 115 VHDL : FSM for Gray Up/Down Counter

Lecture 116 Synthesis : Gray Up/Down Counter

Lecture 117 Applying Constraints to FSM Gray Updown Counter

Lecture 118 VHDL Test Bench : Gray Up/Down Counter

Lecture 119 Behavioral Simulation - FSM Gray Up-Down Counter

Section 35: Using Generate Construct

Lecture 120 VHDL : Using Generate for N- Bit Shift Register

Lecture 121 Synthesis : N-Bit Shift Register using Generate Construct

Lecture 122 Test Bench : N - Bit Shift Register using Generate Construct

Lecture 123 Simulation : N Bit Shift Register using Generate Construct

Section 36: Using Block Construct

Lecture 124 VHDL : Digital Design Using Block Construct

Lecture 125 Synthesis : Digital Design Using Block Construct

Section 37: About Subprogram - Function & Procedure

Lecture 126 SubProgram - Function & Procedure

Section 38: Using SubProgram : Function

Lecture 127 VHDL : Using Function for N-Bit Adder Design

Lecture 128 Synthesis : Using Function for N-Bit Adder Design

Lecture 129 Test Bench : Using Function for N-Bit Adder Design

Lecture 130 Simulation : Using Function for N-Bit Adder Design

Section 39: Using SubProgram - Procedure

Lecture 131 VHDL : Using Procedure for N-Bit Adder Design

Lecture 132 Synthesis : Using Procedure for N-Bit Adder Design

Lecture 133 Test Bench : Using Procedure for N-Bit Adder Design

Lecture 134 Simulation : Using Procedure for N-Bit Adder Design

Section 40: Multiplier Design

Lecture 135 VHDL : Binary Multiplier

Section 41: VHDL - ( Xilinx FPGA ) A.L.U. Design ( Arithmetic & Logic Unit )

Lecture 136 VHDL - ALU Design ( Behavioral )

Lecture 137 Synthesis - ALU

Lecture 138 VHDL Test Bench - ALU

Lecture 139 Behavioral Simulation - ALU

Section 42: VHDL(Xilinx FPGA) Memory Design-ROM Unit Design

Lecture 140 VHDL - ROM Unit Design

Lecture 141 VHDL Test Bench - ROM Unit

Lecture 142 Synthesis - ROM Unit

Lecture 143 Behavioral Simulation - ROM Unit

Section 43: VHDL(Xilinx FPGA) Memory Design-RAM Unit Design

Lecture 144 VHDL - RAM Unit Design

Lecture 145 VHDL Test Bench - RAM Unit

Lecture 146 Synthesis - RAM Unit

Lecture 147 Behavioral Simulation - RAM Unit

Section 44: Techniques for Integrating VHDL Project (Xilinx FPGA)

Lecture 148 VHDL- Logic 1st

Lecture 149 VHDL - Logic 2nd

Lecture 150 VHDL - Project Integration

Lecture 151 VHDL Test Bench - Integrated Project

Section 45: Career Options : Overview

Lecture 152 Career Options in VHDL Programming , FPGA Design - Overview

Section 46: Starting with the Basics of PCB & PCB Design

Lecture 153 Introduction to PCB & PCB Design

Lecture 154 Introduction to PCB Board

Lecture 155 Electronic Components & Dimensions / Footprints

Section 47: Features of EasyEDA PCB Design Software Tool

Lecture 156 Create your Account to Access EasyEDA PCB Design OnLine Software

Lecture 157 Introduction : Features of EasyEDA PCB Design Software Tool

Section 48: First PCB Design Project with Basic Design Flow

Lecture 158 First PCB Design Project Example : Basic Design Flow

Lecture 159 Basics : Component Placement ( PCB Layout ) & Track Routing ( PCB Design )

Section 49: Schematic Design - For Single Layer PCB

Lecture 160 Schematic Design - Dual DC Power Supply

Lecture 161 Adding Details to Schematic Design

Section 50: Component Placement in a PCB Design

Lecture 162 Component Placement Guidelines for 1 Layer PCB Design

Lecture 163 Component Placement ( PCB Layout ) : Dual DC Power Supply

Section 51: Track Routing in a PCB Design

Lecture 164 Track Routing Guidelines for 1 - Layer PCB

Lecture 165 Track Routing Methods in PCB Design

Section 52: Track Routing - Single Layer PCB Design

Lecture 166 Single Layer PCB Design ( Track Routing )

Section 53: Grounding in PCB Design

Lecture 167 Grounding Techniques in 1 Layer PCB Design

Section 54: Design Rule Check

Lecture 168 DRC - Design Rule Check

Section 55: Cross Probing Feature

Lecture 169 Cross Probing in PCB Design

Section 56: Auto Router Feature

Lecture 170 Auto Router for 1 Layer PCB Design

Section 57: Single Layer ( SMT - Surface Mount ) PCB Design

Lecture 171 Schematic Design - For Single Layer SMT PCB Design

Lecture 172 Component Placement : Single Layer SMT PCB Design

Lecture 173 Track Routing - Single Layer SMT PCB Design

Section 58: Designing Single Layer SMT to Through Version Type PCB

Lecture 174 Designing a New Version : From Single Layer SMT to Through Hole Type PCB

Section 59: PCB Design Project with Directly using PCB Tool ( Without using Schematic Tool )

Lecture 175 Creating a PCB Design Project without using Schematic Tool

Section 60: PCB Artwork & Small PCB Fabrication Setup for Single Layer PCB

Lecture 176 PCB Artwork

Lecture 177 Solder Mask Layer

Lecture 178 Silk Screen Layer ( Legend )

Lecture 179 About Small PCB Fabrication Setup ( For 1 Layer PCB )

Section 61: Double Sided PCB Design : Basic Case Study

Lecture 180 Schematic Design : For Double Sided PCB

Lecture 181 Component Placement

Lecture 182 Track Routing : Double Layer / Double Sided PCB

Beginners , Hobbyists , Teachers & anyone who is interested to Learn to Create Digital Logic Designs , using FPGA / CPLD . University Students , Students from Engineering colleges & Polytechnic Institutes , who want to create the Design for their Programmable Electronics based Academic Project . Anyone who wants to make career in FPGA , VHDL Programming . Electronic Designers / Embedded Engineers / Electronic Circuit Design Professionals , who are new to VHDL Programming & FPGA / CPLD Device Architectures .