Asynchronous Sequential Circuit Design And Analysis

ABSTRACT
Asynchronous Sequential Machine Design and Analysis provides a lucid, in-depth treatment of asynchronous
state machine design and analysis presented in two parts: Part I on the background fundamentals
related to asynchronous sequential logic circuits generally, and Part II on self-timed
systems, high-performance asynchronous programmable sequencers, and arbiters.
Part I provides a detailed review of the background fundamentals for the design and analysis of
asynchronous finite state machines (FSMs). Included are the basic models, use of fully documented
state diagrams, and the design and characteristics of basic memory cells and Muller C-elements.
Simple FSMs using C-elements illustrate the design process. The detection and elimination of timing
defects in asynchronous FSMs are covered in detail. This is followed by the array algebraic approach
to the design of single-transition-time machines and use of CAD software for that purpose,
one-hot asynchronous FSMs, and pulse mode FSMs. Part I concludes with the analysis procedures
for asynchronous state machines.
Part II is concerned mainly with self-timed systems, programmable sequencers, and arbiters. It
begins with a detailed treatment of externally asynchronous/internally clocked (or pausable) systems
that are delay-insensitive and metastability-hardened. This is followed by defect-free cascadable
asynchronous sequencers, and defect-free one-hot asynchronous programmable sequencers—their
characteristics, design, and applications. Part II concludes with arbiter modules of various types,
those with and without metastability protection, together with applications.
Presented in the appendices are brief reviews covering mixed-logic gate symbology, Boolean
algebra, and entered-variable K-map minimization. End-of-chapter problems and a glossary of
terms, expressions, and abbreviations contribute to the reader’s learning experience. Five productivity
tools are made available specifically for use with this text and briefly discussed in the Preface.