System Design Using Vhdl

FPGA Based Design

What you'll learn

Learners can understand the difference between various PLDs

Learners can understand various construct of VHDL

Learners can start writing VHDL Code for combinational digital circuits

Learners can start writing VHDL Code for sequential digital circuits

Requirements

No programming knowledge needed

Description

After completion of this course learners will be able to:(1) Understand the concepts of design metrics which are to be optimized by a design engineer(2) Understand the concepts of IC design technology(3) Understand the implementation of logic using Fixed Function IC Technology, Full Custom ASIC Technology, and Semi-Custom ASIC Technology(4) Understand the advantages and disadvantages of implementation of logic using Fixed Function IC Technology, Full Custom ASIC Technology, and Semi-Custom ASIC Technology(5) Understand the concept of implementation of logic in PLAs, PALs, and CPLDs(6) Understand the concept of implementation of logic in FPGAs(7) Understand the IC design flow(8) Understand the role of HDL in system design(9) Understand the concepts of various VHDL constructs(10) Understand various operators and their uses in VHDL coding(11) Understand how to use Xilinx software for writing a VHDL code(12) Understand how to use Xilinx software for simulating a VHDL code(13) Understand how to use Xilinx software for implementing a VHDL code(14) Implement combinational logic by using a behavioral modeling style(15) Implement combinational logic by using a dataflow modeling style(16) Implement combinational logic by using a structural modeling style(17) Implement sequential logic by using a behavioral modeling style(18) Implement sequential logic by using a structural modeling style

Overview

Section 1: IC Design Technology

Lecture 1 Introduction to course

Lecture 2 Design Metrics

Lecture 3 Fixed Function IC Technology

Lecture 4 Full Custom ASIC Technology

Lecture 5 Semi-Custom ASIC Technology

Lecture 6 HDL Role in System Design

Lecture 7 PLD Technology (PLA)

Lecture 8 PLD Technology (PAL) - I

Lecture 9 PLD Technology (PAL) - II

Lecture 10 CPLD

Lecture 11 FPGA (Architecture)

Lecture 12 FPGA (Logic Implementation Examples)

Section 2: Basic Elements of VHDL

Lecture 13 History of VHDL

Lecture 14 Introduction of VHDL

Lecture 15 Data Object - I

Lecture 16 Data Object - II

Lecture 17 Data Object - III

Lecture 18 Data Types - I

Lecture 19 Data Types - II

Lecture 20 Data Types - III

Lecture 21 Data Types - IV

Lecture 22 Data Types - V

Lecture 23 Data Types - VI

Lecture 24 Operators - I

Lecture 25 Operators - II

Lecture 26 Operators - III

Lecture 27 Operators - IV

Lecture 28 Operators - V

Lecture 29 Operators - VI

Lecture 30 Operators - VII

Lecture 31 Operators - VIII

Section 3: Behaviour Modelling

Lecture 32 Introduction to Behavior Model

Lecture 33 Behavior Model (Example)-I

Lecture 34 Behavior Model (Example)-II

Lecture 35 Testbench-I

Lecture 36 Testbench-II

Lecture 37 Behavior Model – Some concepts

Lecture 38 Behavior Model Full Adder (Alternate Code)

Lecture 39 Behavior Model (2 to 1 Multiplexer)

Lecture 40 Behavior Model (1-Bit Comparator)

Lecture 41 Behavior Model (2 to 4 Decoder)

Lecture 42 if-else statements

Lecture 43 Level Triggered D Flip Flop using if-else statement

Lecture 44 2 to 1 Multiplexer using if-else statement

Lecture 45 4 to 1 Multiplexer using if-else statement

Lecture 46 Half Adder using if-else statement

Lecture 47 Full Adder using if-else statement

Lecture 48 1-Bit Comparator using if-else statement

Lecture 49 2-Bit Comparator using if-else statement

Lecture 50 Introduction to “case” Statement

Lecture 51 2 to 1 Multiplexer using case Statement

Lecture 52 4 to 1 Multiplexer using case Statement

Lecture 53 1-Bit Comparator using case Statement

Lecture 54 2 to 4 Decoder using case Statement

Lecture 55 Half Adder using case Statement

Section 4: Dataflow Model

Lecture 56 Dataflow model of AND gate

Lecture 57 Dataflow model of Half and Full Adder

Lecture 58 Dataflow model of Full Adder (Alternate Method)

Lecture 59 Dataflow model of 2-to-4 Decoder

Lecture 60 Dataflow model of 2-to-1 Mux (using Conditional Signal Assignment Statement)

Lecture 61 Dataflow model of 4-to-1 Mux (using Conditional Signal Assignment Statement)

Lecture 62 Dataflow model of 1-Bit Comparator (using Conditional Signal Assig. Statement)

Lecture 63 Dataflow model of 2-to-1 Mux (using Select Signal Assignment Statement)

Lecture 64 Dataflow model of 4-to-1 Mux (using Select Signal Assignment Statement)

Lecture 65 Dataflow model of 1-Bit Comparator (using Select Signal Assignment Statement)

Section 5: Structural Model

Lecture 66 Introduction to Structure Model

Lecture 67 Half Adder Structure Model

Lecture 68 Full Adder Structure Model

Lecture 69 2 to 1 Multiplexer Structure Model

Lecture 70 2 to 4 Decoder Structure Model

Lecture 71 1-Bit Comparator Structure Model

Lecture 72 3-Bit Adder Structure Model

Lecture 73 4 to 1 multiplexer using 2 to 1 Multiplexer

Section 6: Sequential Circuits VHDL Modelling

Lecture 74 D Flip flop VHDL Model-I

Lecture 75 D Flip flop VHDL Model-II

Lecture 76 Jk Flip Flop VHDL Model-I

Lecture 77 Jk Flip Flop VHDL Model-II

Lecture 78 T Flip Flop VHDL Model

Lecture 79 PIPO Behavior Model

Lecture 80 PIPO Structure Model

Lecture 81 SIPO Behavior Model

Lecture 82 SIPO Structure Model

Lecture 83 SISO Structure Model

Lecture 84 SISO Behavior Model

Lecture 85 VHDL Code for Counters

Students who are interested to write and simulate VHDL codes for combinational and sequential circuits,Electronic Engineering Diploma, Under Graduate and Post Graduate students