Introduction To Vhdl

Understand VHDL and how it is used to describe digital circuits

What you'll learn
Implement their own VHDL designs on a FPGA / CPLD
Interpret a digital design written in VHDL
Simulate their own VHDL designs
Understanding of the capabilities of VHDL
Requirements
You should have a basic knowledge of digital logic gates
You should be comfortable with using a computer
Download & install Vivado (the link is provided in the course)
Download & install ModelSim (the link is provided in the course)
Description
Introduction to VHDL is a course that someone with no experience or knowledge of VHDL can use to learn and understand the VHDL language. In this course students will learn about all of the different data types associated with the VHDL language. This course focuses on teaching students how the syntax of VHDL is interpreted and how it can be used to design circuits. There are over 8 different examples digital designs implemented in VHDL.Course StructureThis course starts out by explaining the background and history of VHDL and it's uses. Then students will learn about all the different objects and data types associated with VHDL. There are various examples showing the data types in use and how different objects behave in different applications. After learning about the data types and objects, students will then learn about the keywords and syntax of the VHDL language. Then students will learn about all of the different design architectures used in VHDL. Students will also learn how to design a test bench to simulate and verify functionality of their designs. This knowledge will then be used to complete the final project, tying in all facets of the VHDL language.VHDL DesignsThis course has many design examples, upon completing this course students will have their own library of VHDL design they can use and refer to at any time! This design library includes:Logical AND gateLogical OR gateLogical NOR gateLogical NAN gateLogical XOR gateHalf AdderFull AdderD Flip-FlopDigital ComparatorSR (Set Reset) Latch2:1 MultiplexerPriority EncoderFinal ProjectThe final project in the course has students go through the design process of implementing a priority encoder on their very own development board. This project takes students through the various phases of developing a digital design, testing it, and implementing it. Students will be taken through step-by-step everything that is required to get the priority encoder up and running on their development board.Feel free to message me with any questions before signing up for this course!

Overview

Section 1: Introduction

Lecture 1 Welcome to the Course

Lecture 2 Background

Lecture 3 VHDL Usage Example 1 - Circuit Simulation

Section 2: Objects

Lecture 4 Objects

Lecture 5 Signals

Lecture 6 Signal Example

Lecture 7 Variables

Lecture 8 VHDL Variable Example

Lecture 9 Constants

Lecture 10 Files

Section 3: Data Types

Lecture 11 Standard Logic 1164

Lecture 12 Standard Logic Text IO Package

Lecture 13 Standard Logic Arithmetic

Lecture 14 Numeric Bit

Section 4: Loops and Statements

Lecture 15 IF Statement

Lecture 16 CASE Statement

Lecture 17 LOOP Statement

Lecture 18 NEXT Statement

Lecture 19 EXIT Statement

Section 5: Design Structure

Lecture 20 Entity Example 1 - Digital Logic Circuit

Lecture 21 Entity Example 2 - Multiplexer

Lecture 22 Architecture Example 1 - Digital Logic Circuit

Lecture 23 Architecture Example 2 - Multiplexer

Section 6: Data Flow Design Style

Lecture 24 Logic Gate VHDL Implementations

Lecture 25 AND Gate VHDL Design

Lecture 26 OR Gate VHDL Design

Lecture 27 Half Adder Data Flow Design

Lecture 28 Full Adder Dataflow Design

Section 7: Behavioral Design Style

Lecture 29 Full Adder Behavioral Design

Lecture 30 D Flip-Flop Behavioral Design

Lecture 31 Comparator Behavioral Design

Section 8: Structural Design Style

Lecture 32 Full Adder Structural Design

Lecture 33 Set-Reset Latch Structural Design

Lecture 34 2:1 Multiplexer Structural Design

Section 9: Test Bench Designs

Lecture 35 Full Adder Test Bench Design

Lecture 36 D Flip-Flop Test Bench Design

Section 10: Simulations

Lecture 37 AND Gate ModelSim Simulation

Lecture 38 AND Gate Vivado Simulation

Lecture 39 OR Gate ModelSim Simulation

Lecture 40 OR Gate Vivado Simulation

Lecture 41 D-Flip Flop ModelSim Simulation

Lecture 42 D Flip-Flop Vivado Simulation

Lecture 43 Full Adder ModelSim Simulation

Lecture 44 Full Adder Vivado Simulation

Section 11: FPGA Development Flow Project Using VHDL

Lecture 45 Priority Encoder VHDL Design

Lecture 46 Priority Encoder Test Bench Design

Lecture 47 Priority Encoder Vivado Simulation

Lecture 48 Priority Encoder IO Assignments

Lecture 49 Priority Encoder Synthesis and Implementation

Lecture 50 Priority Encoder Generating Bitstream

Lecture 51 Program and Configure Your FPGA

Lecture 52 Test Design on the FPGA

Section 12: Conclusion

Lecture 53 Appendix A: Reading VHDL BNF

Lecture 54 Conclusion

Anyone who wants to understand VHDL,Anyone who wants to create their own VHDL designs,Anyone who wants to implement designs inside an FPGA or CPLD,Anyone who wants to know how to simulate digital designs using VHDL,Electrical engineers