Digital Electronics - Complete Course (72+ Hours)

Boolean Algebra, K-Maps, Combinational Circuits, Sequential Circuits, Memories.

What you'll learn
Digital Electronics
Logic Gates, Multiplexers, Flip Flops, Semiconductor Memories
Indepth Knowledge of Each Topic
More than 70 Hours of Content
Requirements
No Prior Experience Needed.
Description
1. This Course is for Students having background in Electronics and Telecommunication or any relevant stream.2. This Course is also called as Digital Circuits.3. If you have any experience in any Circuit Design Course prior to this then you can have a look.4. The Prerequisites required are mentioned in the Course Introduction Video.5. This is a Theoretical and Analytical Course.6. This Course is exclusively made from Beginners point of view.7. If you want to learn building Circuits Design Sense and Logic.8. Solutions of Each Problem will be in Detail.8. You will be able to learn different topics with this Course like Combinational Circuits, Sequential Circuits.9. You will be able to handle any Problem in Digital Design after finishing this Course.Digital Design is one of the most core Designs in the Field of Electronics – You can get a Job by just Learning Digital Design.Q:- Will the course teach me Analog Design?A:- No, This topic is dealt in separate Course called Analog Electronics, and they require separate Attention all together.With over 3+ Years of Experience and a 4.0 Instructor Rating in Udemy, I am Coming Up with Core Electronics Course of more than 50+ Hours of Theory and Problem Solving called Digital Electronics - Complete Course (72+ Hours).The curriculum was developed over a period of 2 years.If you are satisfied in any way, Check out my other Courses as well.So what are you waiting for? Click the buy now button and join me on this Wonderful course.

Overview

Section 1: Introduction

Lecture 1 Introduction

Section 2: Logic Gates

Lecture 2 Logic Gates Introduction

Lecture 3 AND Gate

Lecture 4 OR Gate

Lecture 5 NOT Gate (Part 1)

Lecture 6 NOT Gate (Part 2)

Lecture 7 Examples on MultiVibrator

Lecture 8 Small Note

Lecture 9 Universal Gates

Lecture 10 NAND Gate

Lecture 11 Basic gates from NAND

Lecture 12 NOR Gate

Lecture 13 Basic gates from NOR

Lecture 14 EX-OR

Lecture 15 EX-OR Property

Lecture 16 EX-NOR

Lecture 17 EX-NOR Property

Lecture 18 More Properties

Section 3: Boolean Algebra and Reduction Techniques

Lecture 19 Introduction and Few Laws

Lecture 20 Some More Laws

Lecture 21 Consensus Law

Lecture 22 De-Morgans Law

Lecture 23 Duality

Lecture 24 Total Possible Functions

Lecture 25 Self Duality

Lecture 26 Complement of a Function

Lecture 27 Representation of Boolean Expression

Lecture 28 Standard (Canonical) Form

Lecture 29 Minterms

Lecture 30 Another Example

Lecture 31 Shortcut

Lecture 32 MSB LSB

Lecture 33 Max Terms

Lecture 34 Motivation for K Maps

Lecture 35 K-Maps (Intro)

Lecture 36 2-Variable K Map (1)

Lecture 37 2-Variable K Map (2)

Lecture 38 2-Variable K Map (3)

Lecture 39 3-Variable K Map

Lecture 40 4-Variable K Map (1)

Lecture 41 4-Variable K Map (2)

Lecture 42 POS and Another way of Filling

Lecture 43 Examples 4 Variables

Lecture 44 Dont Care

Lecture 45 SOP equals POS

Lecture 46 Another Example for Dont Care Terms

Lecture 47 5 Variable K-Maps

Lecture 48 5 Variable K Map (SOP Example)

Lecture 49 5 Variable K Map (POS Example)

Lecture 50 Implicants

Lecture 51 Prime Implicants

Lecture 52 Essential Prime Implicants

Lecture 53 Some Examples

Lecture 54 Redundant Prime Implicants

Lecture 55 Selective Prime Implicants

Section 4: Boolean Arithmatic

Lecture 56 Representation of Numbers

Lecture 57 Decimal to Binary

Lecture 58 Decimal to Binary (2)

Lecture 59 Binary to Decimal

Lecture 60 Octal Number System

Lecture 61 Octal Conversions

Lecture 62 Hexadecimal Number System

Lecture 63 Binary Addition

Lecture 64 Binary Subtraction

Lecture 65 Binary Multiplication

Lecture 66 Binary Division

Lecture 67 Octal Addition

Lecture 68 Octal Addition (Standard)

Lecture 69 Octal Subtraction

Lecture 70 Octal Multiplication

Lecture 71 Octal Division

Lecture 72 Octal Division (Standard)

Lecture 73 Hexadecimal Number System (2)

Lecture 74 Hexadecimal to Decimal

Lecture 75 Decimal to Hexadecimal

Lecture 76 Hexadecimal to Binary

Lecture 77 Binary to Hexadecimal

Lecture 78 Hexadecimal to Octal

Lecture 79 Octal to Hexadecimal

Lecture 80 Hexadecimal Addition

Lecture 81 Hexadecimal Subtraction

Lecture 82 Hexadecimal Multiplication

Lecture 83 Hexadecimal Division

Lecture 84 Websites for Conversions

Lecture 85 Codes

Lecture 86 Morse Code

Lecture 87 BCD Code

Lecture 88 Gray Code

Lecture 89 Reflection of Gray Code

Lecture 90 Binary to Gray Conversion

Lecture 91 Gray to Binary Conversion

Lecture 92 Excess-3 Code

Lecture 93 2421 Code

Lecture 94 BCD Addition (Intro)

Lecture 95 BCD Addition Rules

Lecture 96 BCD Addition (Case 1)

Lecture 97 BCD Addition (Case 2)

Lecture 98 BCD Addition (Case 3)

Lecture 99 BCD Addition (Case 4)

Lecture 100 Signed Number Representation

Lecture 101 Sign Magnitude

Lecture 102 Range of Sign Magnitude

Lecture 103 1's Compliment Representation

Lecture 104 7's Compliment Representation

Lecture 105 9's Compliment Representation

Lecture 106 F's Compliment Representation

Lecture 107 r's Compliment Representation

Lecture 108 Signed Representation Example of Negative Decimal Number

Lecture 109 Signed Representation Example of Positive Decimal Number

Lecture 110 Signed Representation in Other Number Systems

Lecture 111 Another way of 2's Complement

Lecture 112 Special Case of 2's Compliment

Lecture 113 Rules of Complement Arithmatic

Lecture 114 Examples on Complement Arithematic

Lecture 115 More Examples (2)

Lecture 116 More Examples (3)

Lecture 117 More Examples (4)

Lecture 118 More Examples (5)

Lecture 119 More Examples (6)

Lecture 120 Overflow

Lecture 121 Overflow (Another Approach)

Lecture 122 Range of Binary Representation

Lecture 123 A Table of Representation

Lecture 124 Other Base Arithematic

Lecture 125 Other Base Arithematic (2)

Section 5: Combinational Circuits

Lecture 126 Combinational Circuits Introduction

Lecture 127 Design Procedure of Combinational Circuit

Lecture 128 Design Example of Combinational Circuit

Lecture 129 Design Example (2)

Lecture 130 Design Example (3)

Lecture 131 Another way of Representating Circuit

Lecture 132 1's Complement Circuit

Lecture 133 Square of a Number

Lecture 134 Sum of Two Numbers

Lecture 135 Half Adder

Lecture 136 Half Adder using NAND

Lecture 137 Half Adder Using NOR

Lecture 138 Full Adder

Lecture 139 Designing Full Adder

Lecture 140 Designing Full Adder using NAND Gate

Lecture 141 Designing Full Adder using NOR Gate

Lecture 142 Half Subtractor

Lecture 143 Half Subtractor (Universal Gates)

Lecture 144 Full Subtractor

Lecture 145 Designing of Full Subtractor

Lecture 146 Designing of Full Subtractor (NAND)

Lecture 147 Designing of Full Subtractor (NOR)

Lecture 148 Binary Adders

Lecture 149 Binary Parallel Adder

Lecture 150 Binary Parallel Adder (Delay)

Lecture 151 Binary Parallel Adder (Example)

Lecture 152 Binary Subtractor

Lecture 153 Binary Parallel Subtractor (Better Design)

Lecture 154 Look Ahead Carry Adder

Lecture 155 Two Step Design in Look Ahead Carry Adder

Lecture 156 Final Circuit of Look Ahead Carry Adder

Lecture 157 Serial Adder

Lecture 158 BCD Adder

Lecture 159 BCD Adder (Partial Circuit)

Lecture 160 BCD Adder (Complete Circuit)

Lecture 161 BCD Subtractor

Lecture 162 Excess-3 (XS-3) Addition

Lecture 163 Excess-3 (XS-3) Representation/Comparison

Lecture 164 Excess-3 Self Complementing Property

Lecture 165 Excess 3 Addition Example

Lecture 166 Excess-3 Addition Circuit

Lecture 167 Excess-3 Subtraction

Lecture 168 Excess-3 Subtraction Circuit (1's Complement)

Lecture 169 Excess-3 Subtraction Circuit (2's Complement)

Lecture 170 Code Converters

Lecture 171 4 Bit Binary to Gray Code Converter

Lecture 172 4 Bit Gray to Binary Code Converter

Lecture 173 4 Bit BCD to Excess-3 Code Converter

Lecture 174 Excess-3 to BCD Code Converter

Lecture 175 4 Bit Binary to BCD Code Converter

Lecture 176 BCD to Binary Code Converter

Lecture 177 7 Segment Display

Lecture 178 7 Segment Display (Design Example)

Lecture 179 7 Segment Display (Design Example 2)

Lecture 180 Two Digit Seven Segment Display

Lecture 181 Parity Generator and Checker Introduction

Lecture 182 Four Bit Even Parity Generator

Lecture 183 Four Bit Odd Parity Generator

Lecture 184 Four Bit Even Parity Checker

Lecture 185 Four Bit Odd Parity Checker

Lecture 186 Three Bit Parity Generator and Checker

Lecture 187 1-Bit Magnitude Comparator

Lecture 188 2-Bit Magnitude Comparator

Lecture 189 Problem in Magnitude Comparator

Lecture 190 2-Bit Magnitude Comparator (Alternate Approach)

Lecture 191 2-Bit Magnitude Comparator (Alternate Approach) Circuit

Lecture 192 3 and 4 Bit Magnitude Comparator

Lecture 193 2 Bit Comparator Using 1 Bit Comparator

Lecture 194 3 Bit Comparator Using 1 Bit Comparator

Lecture 195 3-Bit Magnitude Comparater Using 2-Bit and 1-Bit Comparator

Lecture 196 4-Bit Magnitude Comparator Using 1-Bit Magnitude Comparator

Lecture 197 4-Bit Magnitude Comparator Using 2/3-Bit Magnitude Comparator

Lecture 198 Summary of Magnitude Comparator

Lecture 199 Decoder (Introduction)

Lecture 200 2x4 Decoder (Active High Output)

Lecture 201 2x4 Decoder Circuit (Active High Output)

Lecture 202 2x4 Decoder Circuit (Active Low Output)

Lecture 203 3x8 Decoder Circuit (Active High Output)

Lecture 204 3x8 Decoder Circuit (Active Low Output)

Lecture 205 4x16 Decoder Using 3x8 Decoder

Lecture 206 4x16 Decoder Using 2x4 Decoder

Lecture 207 5x32 Decoder

Lecture 208 1x2 Decoder

Lecture 209 Full Adder Using Decoders

Lecture 210 BCD to 7-Segment Display (Decoder Version)

Lecture 211 BCD to 7-Segment Display (Active Low Decoder Version)

Lecture 212 Overall Active Low Output in Decoder Design

Lecture 213 Summary of Combinational Circuit using Decoder

Lecture 214 Encoder (Introduction)

Lecture 215 4x2 and 8x3 Encoder

Lecture 216 16x4 Encoder

Lecture 217 Motivation for Priority Encoder

Lecture 218 2x1 Priority Encoder

Lecture 219 4x2 Priority Encoder

Lecture 220 4x2 Priority Encoder with Enable

Lecture 221 8x3 Priority Encoder With and Without Enable

Lecture 222 8x3 Priority Encoder Circuit

Lecture 223 Summary of Encoder and Priority Encoder

Lecture 224 Octal to Binary Encoder

Lecture 225 Octal to Binary Priority Encoder

Lecture 226 Decimal to BCD Encoder

Lecture 227 Decimal to BCD Priority Encoder

Lecture 228 Binary to Gray Code Converter Using Encoder

Lecture 229 BCD to Excess-3 Code Converter Using Encoder

Lecture 230 Multiplexer Introduction

Lecture 231 2x1, 4x1, 8x1 Multiplexer

Lecture 232 Multiplexers with Enable

Lecture 233 4x1 Mux Using 2x1 Mux

Lecture 234 8x1 Mux Using 4x1 and 2x1

Lecture 235 16x1 Multiplexer

Lecture 236 Basic Gates from Multiplexer

Lecture 237 Full Adder Using 8x1 Mux

Lecture 238 Full Adder Using 4x1 Mux

Lecture 239 Full Adder Using 2x1 Mux

Lecture 240 Another Example of Designing with Multiplexer

Lecture 241 Demultiplexer

Lecture 242 Few Extra Points About Demultiplexer

Lecture 243 Hazards (Introduction)

Lecture 244 Static Hazards

Lecture 245 Static Hazard Example (Case 1)

Lecture 246 Static Hazard Example (Case 2 and Case 3)

Lecture 247 Static Hazard Example 2

Lecture 248 Conclusion of Static Hazard Examples

Lecture 249 Static Hazard Example-1 Using K-Maps

Lecture 250 Static Hazard Example-2 Using K-Maps

Lecture 251 Static Hazard Example-3

Lecture 252 Dynamic Hazard

Section 6: Flip Flops and Registers

Lecture 253 Sequential Circuits Introduction

Lecture 254 Flip Flop and Latches

Lecture 255 Active High SR Latch Using NOR

Lecture 256 Active Low SR Latch Using NOR

Lecture 257 Active Low SR Latch Using NAND

Lecture 258 Active High SR Latch Using NAND

Lecture 259 SR Latch Conclusion

Lecture 260 JK Latch Using NOR Gate

Lecture 261 JK Latch Using NAND Gate

Lecture 262 D-Latch and T-Latch

Lecture 263 Clock Signal

Lecture 264 Level Triggering

Lecture 265 Edge Triggering

Lecture 266 SR Gated Latch Using NOR Gate (Active High)

Lecture 267 SR Gated Latch Using NOR Gate (Active Low)

Lecture 268 SR Gated Latch Using NAND Gate

Lecture 269 JK Gated Latch Using NOR Gate

Lecture 270 JK Gated Latch Using NAND Gate

Lecture 271 D Gated Latch

Lecture 272 T Gated Latch

Lecture 273 Race Around Condition

Lecture 274 Master Slave Configuration

Lecture 275 Other Master Slave Configurations

Lecture 276 Edge Triggering Circuit

Lecture 277 Review of Flip Flop and Latches

Lecture 278 SR Flip Flop

Lecture 279 JK D and T Flip Flop

Lecture 280 Asynchronous Input (Intro)

Lecture 281 Asynchronous Inputs Truth Table

Lecture 282 Different Representation of Asynchronous Input

Lecture 283 Conversion of Flip Flops

Lecture 284 SR to JK Flip Flop Conversion

Lecture 285 More Examples on Conversion of FF

Lecture 286 Convert XY FF Using JK FF

Lecture 287 Propagation Delay of Flip Flop

Lecture 288 Setup Time and Hold Time (Part-1)

Lecture 289 Setup Time and Hold Time (Part-2)

Lecture 290 Setup Time and Hold Time (Part-3)

Lecture 291 Clock Skew

Lecture 292 Registers

Lecture 293 Serial In Serial Out Shift Registers

Lecture 294 Serial In Parallel Out Shift Register

Lecture 295 Parallel In Shift Registers

Lecture 296 Summary Shift Registers

Lecture 297 Rotate Right Rotate Left Shift Registers

Lecture 298 Bi-Directional Shift Registers

Lecture 299 Universal Shift Registers

Lecture 300 Counters Introduction

Lecture 301 Asynchronous Counter Introduction

Lecture 302 2-Bit Up Counter

Lecture 303 2-Bit Down Counter

Lecture 304 2-Bit Up-Down Counter (Positive Edge)

Lecture 305 3-Bit Up Counter

Lecture 306 3-Bit Down Counter

Lecture 307 3-Bit Up Down Counter (Positive Edge)

Lecture 308 Summary of Asynchronous Counter

Lecture 309 Non-Binary Asynchronous Counters

Lecture 310 Non-Binary Asynchronous Counters (with Preset)

Lecture 311 Decoding Error (Glitches or Spikes)

Lecture 312 Solution of Decoding Error

Lecture 313 Caution in Asynchronous Counter

Lecture 314 Synchrounous Counter (Introduction)

Lecture 315 Design Procedure of Synchronous Counter

Lecture 316 Synchronous Counter Example-1

Lecture 317 Synchronous Counter Example-2

Lecture 318 Synchronous Counter Example-3

Lecture 319 Value of Counter for 'x' Cycles

Lecture 320 Synchronous Counter Example-4

Lecture 321 Analysis of Synchronous Counter (Example-4)

Lecture 322 Lockout Problem

Lecture 323 Synchronous Counter Example-5

Lecture 324 Ring Counter

Lecture 325 Ring Counter Lockout Problem

Lecture 326 Advantages of Ring Counter

Lecture 327 Twisted Ring Counter

Lecture 328 Twisted Ring Counter Lockout Problem

Lecture 329 Final Point on Ring and Twisted Ring Counter

Lecture 330 Delays in Synchronous Counters

Lecture 331 Sequence Generator

Lecture 332 Analysis of Sequence Generator

Lecture 333 Sequence Generator (Example-2)

Lecture 334 [Method-2] Sequence Generator

Lecture 335 [Method-2] Sequence Generation More Examples

Lecture 336 [Method-3] Sequence Generation

Lecture 337 [Method-3] Sequence Generation (Part-2)

Lecture 338 Quick Revision (Sequential Circuit)

Section 7: Sequential Circuits

Lecture 339 Definitions in Sequential Circuits

Lecture 340 State Diagrams and State Tables

Lecture 341 Mealy to Moore and Moore to Mealy

Lecture 342 Mealy to Moore and Moore to Mealy (2)

Lecture 343 State Reduction

Lecture 344 State Reduction (Example-2)

Lecture 345 Designing of Sequential Circuit

Lecture 346 Sequential Circuit (Example-2)

Lecture 347 Sequential Circuit (Example-3)

Lecture 348 Serial Adder (Mealy Machine)

Lecture 349 Serial Adder (Moore Machine)

Lecture 350 Sequence Detector Introduction

Lecture 351 Overlapping and Non Overlapping Output

Lecture 352 Sequence Detector State Diagram (Part-1)

Lecture 353 Sequence Detector State Diagram (Part-2)

Lecture 354 Sequence Detector State Diagram (Part-3)

Lecture 355 Sequence Detector State Diagram (Part-4)

Lecture 356 Sequence Detector State Diagram (Part-5)

Lecture 357 Sequence Detector State Diagram (Part-6)

Lecture 358 Sequence Detector State Diagram (Part-7)

Lecture 359 Sequence Detector State Diagram (Part-8)

Lecture 360 Complete Design of Sequence Detector

Lecture 361 An Elevator

Lecture 362 Two Button Digital Lock

Section 8: Programmable Logic Devices (PLDs)

Lecture 363 Programmable Logic Devices (Introduction)

Lecture 364 Note Points in PLDs

Lecture 365 PAL Examples

Lecture 366 PROM

Lecture 367 PROM Examples (2)

Lecture 368 PLA Example

Lecture 369 PLA Example 2

Lecture 370 Optimized PLA Design Example

Lecture 371 Optimized PLA Design Example 2

Section 9: Analog to Digital and Digital to Analog Converters

Lecture 372 Digital to Analog Converters

Lecture 373 R-2R Ladder DAC

Lecture 374 R-2R Ladder DAC (2)

Lecture 375 Binary Weighted DAC

Lecture 376 Comparison R-2R and Binary Weighted DAC

Lecture 377 Inverted R-2R DAC

Lecture 378 Questions on Inverted R-2R and Binary Weighted

Lecture 379 Switched Capacitor DAC

Lecture 380 Specifications of DAC

Lecture 381 Questions on DAC

Lecture 382 Analog To Digital Converter (Introduction)

Lecture 383 Counter Type ADC

Lecture 384 Questions on Counter Type ADC

Lecture 385 Tracking Type ADC

Lecture 386 Flash Type ADC

Lecture 387 Successive Approximation Type ADC

Lecture 388 Questions on Successive Approximation Type

Lecture 389 Before Dual Slope Integration ADC

Lecture 390 Dual Slope Integrating Type ADC

Lecture 391 Questions on Dual Slope Integrating Type ADC

Lecture 392 Summary of Analog to Digital Conversion

Lecture 393 Sample and Hold Circuit

Lecture 394 Specification of Analog to Digital Converter

Section 10: Logic Families

Lecture 395 Logic Families (Introduction)

Lecture 396 Switching Devices

Lecture 397 Fan Out

Lecture 398 Fan In, Power Dissipation, Propagation Delay, FOM

Lecture 399 Noise Margin

Lecture 400 Questions on Characteristics of Logic Families

Lecture 401 Classification of Logic Family

Lecture 402 Resistor Transistor Logic (RTL)

Lecture 403 Diode Transistor Logic

Lecture 404 Question on Diode Transistor Logic

Lecture 405 High Threshold Logic (HTL)

Lecture 406 Direct Coupled Transistor Logic (DCTL)

Lecture 407 DCTL to I2L

Lecture 408 Integrated Injection Logic Family

Lecture 409 Transistor Transistor Logic (TTL)

Lecture 410 Modified Transistor Transistor Logic (TTL)

Lecture 411 Motivation for Totem Pole Output

Lecture 412 Totem Pole Output

Lecture 413 Open Collector TTL

Lecture 414 Tristate Logic

Lecture 415 Schottky Transistor

Lecture 416 Schottky TTL

Lecture 417 TTL Families Comparison

Lecture 418 Emitter Coupled Logic (ECL)

Lecture 419 Problems in ECL

Lecture 420 Modified ECL

Lecture 421 Wired OR in ECL

Lecture 422 A Question on ECL

Lecture 423 MOS Logic Family (Introduction)

Lecture 424 NMOS As Switch

Lecture 425 NMOS Universal Gates

Lecture 426 PMOS As Switch

Lecture 427 PMOS Universal Gates

Lecture 428 Towards CMOS Logic Family

Lecture 429 CMOS Logic Family

Lecture 430 Example on NMOS PMOS and CMOS Implementation

Lecture 431 Power Dissipation in CMOS

Lecture 432 Pass Transistor Logic

Lecture 433 Transmission Gate

Lecture 434 Comparison of Logic Families

Section 11: Semiconductor Memories

Lecture 435 Classification of Memories

Lecture 436 Read and Write Memory

Lecture 437 SRAM

Lecture 438 DRAM

Lecture 439 3T DRAM Cell

Lecture 440 Diode ROM

Lecture 441 Masked PROM

Lecture 442 EPROM

Lecture 443 EEPROM

Lecture 444 Flash Memory

Section 12: Thank You Note

Lecture 445 What Now?

Lecture 446 Thank You Note!

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