Digital Design From Scratch

Using VHDL in FPGAs from the ground up

What you'll learn
Digital design basics, including logic gates, binary/hexadecimal numbers, registers, shift registers, counters, timing diagrams, propagation/setup/hold timing
VHDL language basics, including VHDL file formats/libraries, coding logic equations, conditional statements, arrays, timing constraints
Coding, including case statements, state machines, coding from timing diagrams, while-loops, standard/unsigned types, VHDL components (modules), simulation
Practical examples: memories (inferred/dual port), FIFOs, memory-mapped buses, serial interfaces (RS232, UARTs, I2C, SPI), DSP, PLLs, Manchester/8B10B encoding
Requirements
A rudimentary understanding of algebra is helpful, but not necessary.
Description
VHDL is a powerful programming language for developing FPGAs, but is useless without an in-depth understanding of digital design. This course provides the student a comprehensive working knowledge of both of these in parallel. VHDL describes digital logic, and, as such, is an ideal vehicle for developing a deep understanding of the functional power available in modern FPGA devices.

Overview

Section 1: Fundamentals

Lecture 1 1.1: Introduction

Lecture 2 1.2: Boolean logic gates, binary state, and timing diagrams

Lecture 3 1.3: traffic light example, coding Boolean equations

Lecture 4 1.4: the latch

Lecture 5 1.5: enabled latches, series operations, and rising-edge pulses

Lecture 6 1.6: process and conditional statements, clocked registers

Lecture 7 1.7: register-to-register transfers, hold/setup time

Lecture 8 1.8: elsif, enabled set/reset flop, propogation delays

Section 2: Functional Design Components

Lecture 9 2.1: binary and hexadecimal numbers

Lecture 10 2.2: shift registers, counters, vectors, and 1k vs. 1K

Lecture 11 2.3: counter in the traffic light application, edge and terminal count detect.

Lecture 12 2.4: coding from timing diagrams

Lecture 13 2.5: introduction to state machines

Lecture 14 2.6: case statements

Lecture 15 2.7: state machines, case statements, and the traffic example

Lecture 16 2.8: coding the simple traffic state machine

Section 3: FPGAs, VHDL, and simulation

Lecture 17 3.1: introduction to FPGAs

Lecture 18 3.2: VHDL head-on, text editors

Lecture 19 3.3: entities and architectures, vector types, and VHDL libraries

Lecture 20 3.4: modular design, debounce, falling-edge detection

Lecture 21 3.5: introduction to simulation

Lecture 22 3.6: simulation testbench, creatiing stimulus

Lecture 23 3.7: introduction to Modelsim, constants, stalling process statements

Lecture 24 3.8: using Modelsim

Section 4: Practical FPGA Elements

Lecture 25 4.1: single and dual-port memories

Lecture 26 4.2: arrays and while loops

Lecture 27 4.3: inferred memories, coded dual-port memory, shared bus RAM, tri-state buffer

Lecture 28 4.4: FIFOs

Lecture 29 4.5: Avalon and AXI memory-mapped buses

Lecture 30 4.6: serial interfaces, RS232, UARTs

Lecture 31 4.7: I2C, SPI, clocks and timing

Lecture 32 4.8: introduction to DSP

Section 5: Bonus: clock recovery in serial interfaces

Lecture 33 Serial interface clock recovery

Entry level students interested in developing programs for FPGAs.,Technicians and engineers who would like to learn VHDL (an FPGA programming language).