Complete Training Design Uart Using Verilog Or Vhdl On Fpga

Design of UART on FPGA using VHDL or verilog HDL programming

What you'll learn
the student will learn how to design a half-duplex and also a full duplex transceiver.
the student will learn about baud rates, how to design one and the different lists of standard baud rates
the student will learn how to design a UART serial communication protocol and implement it on an FPGA Board
design UART transmitter AND receiver on FPGA with vhdl code, and simulate on logism
the student will learn how to convert serial bits to parallel bits and vice versa, and also implement in VHDL
the student will also learn some commonly used VHDL structural blocks like shift registers, parallelizer, serializer,
design UART transceiver on FPGA with vhdl code, and simulate on logism
Requirements
No external hardware needed. We would simulate the FPGA design in logism. Basic knowlegde of vhdl and how to use logism may be required.
Description
This is a practical course, that will teach you how to design your first UART project on FPGA  using Verilog HDL programming language.In this course, you will learn the difference between a full duplex UART transmission and a half-duplex transmission including their technical difference.  You will how to use LOGISM EDA tool to design, test and simulate logic circuits. You will a baud clock, learn how it is synthesized from system clock and how to calculate the frequency of generation.you will learn what a baud rate means and also learn the standard baud rates and how to generate them from the system clock. You will learn how to design and wire the receiver and transmitter to their baud clocks and how they are joined together to make up the transceiver.The course is divided into three sections: the receiver, the baud generator and transmitter.This a 17 video course. each module teaching about a particular part of the design.a lot of visuals, arrows, pictures were used to make the tutorials easy to understand.kindly use the logism circuit file while watching the tutorial for easy understanding. You will get the VHDL scripts and the logism circuit attached to lesson two. No hardware is required just your pc.It was kept brief and straight to the point.

Overview

Section 1: Introduction to UART communication

Lecture 1 01- Introduction

Lecture 2 Download zipped project folder

Lecture 3 02 - How to ask the instructor questions

Lecture 4 03 - UART configuration

Lecture 5 04 - introducing the logism design

Section 2: The Baudrate generator AND parity generator

Lecture 6 05 - How to set baud rate to carryout Oversampling

Lecture 7 06 - How to design the baud generator

Lecture 8 07 - simulating the baud generator in logism and testing oversampling

Lecture 9 How to ask the instructor questions

Lecture 10 08 - How to design and simulate the parity generator used for error check

Section 3: The Receiver

Lecture 11 09 - Design of a UART receiver sub circuit

Lecture 12 10 - testing and simulating the UART receiver in LOGISM PART1

Lecture 13 11 - testing and simulating the UART receiver in LOGISM PART2

Lecture 14 12 - Designing the receiver top circuit and merging it with the baud generator

Lecture 15 How to ask the instructor questions

Section 4: The transmitter

Lecture 16 13 - How to design a UART transmitter

Lecture 17 14 - Simulation and testing of UART transmitter in Logism PART1

Lecture 18 15 - Simulation and testing of UART transmitter in Logism PART2

Lecture 19 16 - How to design the transmitter top and add the baud generator

Section 5: Conclusion

Lecture 20 17 - Assignment and conclusion

Students with basic knowledge of VHDL, looking for a project to design