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  3. Low Power Design with High-Level Power Estimation and Power-Aware Synthesis (repost)

Low Power Design with High-Level Power Estimation and Power-Aware Synthesis (repost)

Posted By: arundhati
Date: 13 Feb 2017 18:30:20
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis (repost)

Sumit Ahuja, Avinash Lakshminarayana and Sandeep Kumar Shukla, "Low Power Design with High-Level Power Estimation and Power-Aware Synthesis"
English | ISBN: 1461408717 | 2012 | 200 pages | PDF | 4 MB

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

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