Intel Quartus Prime Professional Edition 25.1.0 (129)

Comprehensive Support for Agilex 3 FPGAs

The Agilex 3 FPGA family brings high performance, power efficiency, and cost optimization to edge and embedded applications. With this release you can design, test, and deploy solutions more effectively utilizing the Agilex 3 higher-speed transceivers for improved connectivity, on-chip dual Cortex-A55 ARM cores, adding powerful processing capabilities, and expanded memory support, including LPDDR4.

For applications where board space is limited, Agilex 3 utilizes Intel’s variable pitch BGA packaging to enable more compact and efficient designs. This technology allows developers to fit more functionality into smaller footprints while maintaining performance and power efficiency.

Security is essential for protecting intellectual property and sensitive data in FPGA applications. Agilex 3 includes new features that strengthen encryption, authentication, and physical security, making designs more resilient to tampering and attacks.

Nios V Soft Processor Enhancements

The Nios V plays a crucial role in embedded applications, and this release brings performance and efficiency improvements. These updates enable developers to build more compact, higher-performing embedded systems.
- Nios V/g Core Performance Boost –Improved task execution efficiency and optimized overall performance
- Nios V/c Core Area Reduction – Achieves an 8% area reduction, making designs more compact.
- Ashling RISCFree IDE VS Code Extension – Provides a Visual Studio Code extension for streamlined Nios® V software development using Ashling RiscFree IDE.
- TinyML Example Design using Nios V Application Note – Enables developers to integrate machine learning (ML) capabilities into FPGA designs using microcontrollers

Embedded Software Features

FPGA-based embedded applications require robust OS and virtualization support. Quartus Prime Pro 25.1 expands compatibility for Linux, RTOS, and hypervisors, allowing developers to create scalable, real-time, and virtualized embedded solutions.
- Linux Hardware Reference Designs – Standard and regular editions for seamless Linux development.
- Xen Hypervisor Support – Allows developers to build virtualized environments for FPGA applications.
- RTOS Support – Supports Zephyr and Bare Metal, with FreeRTOS coming in Q2 (May release).

Installer Improvements: Faster, More Flexible Setup

Installing FPGA software should be efficient and customizable. Quartus Prime Pro 25.1 improves the installation experience with parallel processing, flexible component selection, and better file management.
- Parallel Installation – Reduces setup time by allowing multiple components to install simultaneously.
- Dynamic Component Selection – Lets users choose only the components they need, optimizing disk space and installation time.

Streaming Debug: High-Speed Hardware Debugging

Effective debugging is key to reducing development cycles. The Streaming Debug IP for Signal Tap provides real-time, high-bandwidth data capture, improving how developers analyze and troubleshoot FPGA designs.
- High-Speed Streaming for Hardware Debugging – Enables efficient data transfer for real-time analysis.
- Configurable Streaming via STP – Use Signal Tap Logic Analyzer (STP) to configure the streaming method and select the appropriate debug host.

Simulation Improvements

Quartus Prime Pro 25.1 introduces new native Altera AXI4 Bus Functional Models (BFMs), delivering improved simulation performance, integration, and long-term support.
- Native Altera AXI4 BFMs – Optimized for Quartus simulation workflows, ensuring better compatibility and performance.
- Seamless Transition – Users can switch to the new Altera AXI4 BFMs without significant modifications, benefiting from tighter toolchain integration.
Quartus Prime Pro 25.1 brings significant simulation performance improvements, particularly for transceiver protocol IP, leading to faster and more efficient debugging and verification.
- Improved Transceiver Protocol IP Simulation – Enhances support for PCIe, Ethernet, Serial Lite, JESD, and other transceiver protocols.
- Beta Models in 25.1 – The new simulation models are in Beta for this release, with a focus on Ethernet and PCIe.
- Enhanced Performance – Improvements of up to 50% or more are typical, reducing simulation time and accelerating verification.

These simulation updates make Quartus Prime Pro 25.1 a more powerful tool for transceiver-based FPGA designs by delivering faster, more efficient simulations and reducing overall verification time.