Cadence SPB OrCAD 16.60.038 Hotfix
Cadence SPB OrCAD 16.60.038 Hotfix | 1.1 Gb
Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released an hotfix 38 for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1103937 PCB_LIBRARIAN VERIFICATION con2con should not have any need for a graphical terminal
1107843 FSP OTHER Support for lrf and lmf in archived project
1123765 CAPTURE GENERAL .OLBlck file not deleted if library is closed in Capture
1169740 FSP OTHER Ability to import "Assigned Pin" column to connect Generic connector and FPGA.
1172641 FSP FPGA_SUPPORT Support for 5SGSMD5K2F40I2N device
1177760 CAPTURE OTHER IC pins cannot be cross probed from Capture to PCB Editor
1195672 ALLEGRO_EDITOR PLACEMENT Place replicate update should update component value text
1206563 FSP GUI Spreadsheet import support for xc3s400afg400
1208169 FSP FPGA_SUPPORT New FPGA model request
1224428 ALLEGRO_EDITOR PLACEMENT Get message "W-(SPMHGE-579): Unable to complete path to circuit for all selections" when updating place replicate circuit
1230064 ALLEGRO_EDITOR INTERACTIV Place replicate is trying to match dimensions
1253986 CONCEPT_HDL CORE Not able to define Source when adding property to a selected group
1266615 ADW SHOPINGCART Error(SPDWUB-48) while placing the part from the shopping cart
1269658 ALLEGRO_EDITOR EDIT_ETCH Ratsnest disappears near pin when routing
1270158 CONCEPT_HDL CONSTRAINT_MGR Orphan nets are visible in CM but not in DE-HDL
1275042 CONCEPT_HDL COMP_BROWSER Unit specifier 'HC' not found in UNITS environment while placing the part on schematic
1276269 ALLEGRO_EDITOR TESTPREP On creating a fixture, a test point is generated but refs are not visible.
1278037 SIP_LAYOUT ASSY_RULE_CHECK DRC soldermask to finger check required for cases when the finger has no wire attached
1278475 ALLEGRO_EDITOR DATABASE Import Logic changes VIA net names to GND
1279162 SIP_LAYOUT DIE_ABSTRACT_IF Add codesign die should default shrink/scribe settings from die abstract if abstract contains this information.
1282358 SIP_LAYOUT OTHER Why are IC/PKG symbols always mirrored when placed on a sip design?
1283439 CAPTURE ANNOTATE Inter Sheet Refs placed on top of Off Page Connector name
1284809 ALLEGRO_EDITOR INTERACTIV Using the Fix icon in the toolbar will not apply the Fixed property to Groups
1286277 CAPTURE SCHEMATICS Capture crashes on adding Bezier curves
1286354 CONCEPT_HDL CORE The GENERATE_SCH_METADATA 'ON' directive causes significant DE-HDL performance degradation
1286617 CONCEPT_HDL CORE Generate View failure
1287020 CAPTURE OTHER Option to disable Autobackup
1287100 FSP DESIGN_SETTINGS FSP global edit of Capture library paths
1287877 CONCEPT_HDL CHECKPLUS Graphic check in CheckPlus hangs with sch_something view
1289056 ADW OTHER MKnet program to also read the alim.auto from ADW_CONF_ROOT
1289107 CONCEPT_HDL CORE Find with Schematic Selection fails after clicking Find All three times
1289175 CAPTURE OPTIONS Autobackup changes timestamp of each and every part in the library.
1289447 TDA CORE Undo Check-out removes new design data from local area
1289677 ALLEGRO_EDITOR SHAPE Complex shape filling fails without DRC
1289755 ALLEGRO_EDITOR EDIT_ETCH Timing Vision Display error
1289913 ALLEGRO_EDITOR EDIT_ETCH Enhance the fanout function to speed up the layout design in Allegro PCB Editor.
1290136 ALLEGRO_EDITOR EDIT_ETCH Unable to connect IC pin to ground
1290426 SIP_LAYOUT LOGIC Deleting a distributed codesign component from parts list does not remove the component information from the design database
1291888 ALLEGRO_EDITOR INTERACTIV Property DYN_DELETED_ISLAND is not added on all the voids created by Delete Island command
1292206 ALLEGRO_EDITOR OTHER Allow netname to be visible for pin/cline when viewed in Allegro PDF Publisher
1292234 APD SHAPE Shape does not Void around Clines and Vias due to some corruption
1292877 ALLEGRO_EDITOR DATABASE DB doctor fixed void boundary but deleted all boundary without detail information.
1293041 ADW COMPONENT_BROWSE Component Browser does not show results if you filter on the PPL and an additional column
1293188 ALLEGRO_EDITOR EDIT_ETCH fanout function(via in pad) deleted the cline & thermal
1293626 CONCEPT_HDL CORE Delete Page command could not delete the dependency file (page2.csd).
1293710 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during copy fanout
1294355 PSPICE SIMULATOR Function "ddt( )" behavior in DC sweep analysis
1295232 CAPTURE SCHEMATIC_EDITOR Remove from group changes not reflected consistently in Part Manager
1295434 ALLEGRO_EDITOR INTERACTIV Enable Pin Name to be imported into a .BRD and display this in the show info output as done in APD and SIP
1296583 ALLEGRO_EDITOR FSP_PINSWAP Crash for FSP Auto Pinswap with PCB Editor
1297095 ADW LRM LRM replaces incorrect part in schematic.
1297685 F2B DESIGNVARI 'Could not open xmodules.dat file' Error during 'Save'.
1297835 ALLEGRO_EDITOR INTERACTIV DFA-Driven Interactive Placement not working correctly for components on bottom side
1297870 SIP_LAYOUT ASSY_RULE_CHECK Wire to Wire Optical short ADRC reports wrong DRC violation
1297994 ALLEGRO_EDITOR INTERACTIV When moving a via and splitting the stack, the via moves off the design work surface.
1298129 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Phase tuning should have option to Allow DRCs
1299050 ADW PCBCACHE Need a way to turn off all project ptf file backup files under flatlib
1299873 CONCEPT_HDL CORE DE-HDL window size and position is not saved on exit
1300101 ALLEGRO_EDITOR GRAPHICS Inconsistency in symbol editor and PCB Editor while showing 3D view
1300557 ALLEGRO_EDITOR EDIT_ETCH Move Component with "Slide Etch" or "Stretch Etch" removes DYN_CLEARANCE_OVERSIZE from clines
1300806 ALLEGRO_EDITOR GRAPHICS Stroke command in 16.6 works differently as compared with earlier versions
1302103 CONCEPT_HDL CONSTRAINT_MGR DE-HDL CM startup time on large hierarchical is extremely large(6-8 min)
1302939 ALLEGRO_EDITOR PARTITION Place replicate modules lost with design partition
1303078 CAPTURE STABILITY Capture crashes on View – Status Bar with no design open
1303106 ALLEGRO_EDITOR SKILL Creating shape with SKILL script does not work on SPB16.5 and SPB16.6.
1303442 ALLEGRO_EDITOR EDIT_ETCH auto-interactive convert corner function crashes PCB Editor
1303921 ADW COMPONENT_BROWSE Datasheets with spaces are not viewable in component browser
1304042 APD LOGIC ERROR(SPMHUT-43):netin command is not working for .mcm.
1304725 ALLEGRO_EDITOR INTERACTIV Value 0 in Allegro Text Setup not valid anymore
1304734 ALLEGRO_EDITOR PADS_IN PADS_IN does not follow the settings in the options file
1304882 CONCEPT_HDL CORE Hierarchy Viewer jumps up to the top on File Save
1305147 ALLEGRO_EDITOR MANUFACT Auto silk result is unstable.
1306323 ALLEGRO_EDITOR INTERACTIV Mirror command does not seem to work correctly.
1306468 ALLEGRO_EDITOR DATABASE Dbdoctor Crash
1307277 SIP_LAYOUT IMPORT_DATA Wants BGA Text-In Wizard to maintain Pad layer set in the text file instead of defaulting to Bottom layer.
1307367 FSP FPGA_SUPPORT FSP user needs 5SGSMD5K3F40I3N/5SGSED6K3F40I3N in FPGA models.
1307478 ALLEGRO_EDITOR MENTOR unable to do PADS Library translation.
1307626 ALLEGRO_EDITOR INTERACTIV Pick window is different for command and from GUI
1307785 ASI_PI GUI Decap Configuration GUI does not update until you deselect then select GND
1308163 SIP_LAYOUT ORBITIO_IF Importing OrbitIO with multiple packages and XDA file into SIP layout results in incomplete data
1308289 SIP_LAYOUT ORBITIO_IF Import OrbitIO into existing SIP database fails. Testing an ECO type of design flow
1309315 CAPTURE ANNOTATE Incremental annotation is not giving correct refdes in case of attached complex hierarchical design
1310614 CONCEPT_HDL CORE Part Manager creates bogus directory on linux system
1311184 CAPTURE NETLIST_ALLEGRO Incorrect warning for DEVICE property value in netlisting.
1311719 ALLEGRO_EDITOR INTERACTIV Allegro Component will not place on the canvas
1311757 CONCEPT_HDL CORE Cannot change a property from instance level to non-instance level
1311848 CONSTRAINT_MGR OTHER PFE is adding a capacitor after creating PI CSet
1312553 CONCEPT_HDL CORE Customer could not add their net property after deleting it.
1313068 APD DIE_ESCAPE die escape gen: Cannot route from pad of Via Structure.
1313239 CONSTRAINT_MGR CONCEPT_HDL Diff pair constraints disappear if xnet is created for them in Editor
1313850 ALLEGRO_EDITOR PLACEMENT Place Replicate ignores fillet at pins
1314207 ALLEGRO_EDITOR OTHER PCB Editor crash when rotating IPF data
1314467 ALLEGRO_EDITOR INTERACTIV With high_speed option selected, PCB Editor crashes on move operation
1314921 ALLEGRO_EDITOR PLACEMENT RATS are wrongly displayed.
1314973 CAPTURE OTHER Cannot cross-probe all pins from Capture
1316295 ALLEGRO_EDITOR OTHER .brd extension is removed after running DB Doctor from PCB Editor Utilities.
1316757 ALLEGRO_EDITOR DRC_CONSTR Spacing constraint error on negative layer
1316959 ALLEGRO_EDITOR PARTITION Exported soft boundary partition2 symbol still cannot move out of partition boundary
1317157 SIP_LAYOUT DIE_STACK_EDITOR After moving the Dies to different layers a Wirebond has changed the connection from the pin to a shape.
1317480 ALLEGRO_EDITOR SYMBOL Allegro DB check "SPMHA1-247 Illegal mirror error"
1317614 ADW COMPONENT_BROWSE Datasheet_Url is not opening the file browser correctly
1317876 APD COLOR APD crashes when executing Color Dialog for Nets
1320028 FSP DE-HDL_SCHEMATIC Error (10002: Cannot find a ppt part that matches the instance properties
1320438 ALLEGRO_EDITOR GRAPHICS Could not save DFA spreadsheet
1322600 CONCEPT_HDL CONSTRAINT_MGR Cannot extract xnet topology due to missing model even if the model is present
1323327 CONCEPT_HDL CONSTRAINT_MGR Deleting Ref Electrical CSet from Diff Pair removes it from a Matched Group in DE-HDL
1325230 CONCEPT_HDL CORE DE-HDL crashes once the design is loaded.
1325644 F2B PACKAGERXL CDS_LOCATION/$PN not deleted from property file(dcf) backannotation warnings
1325905 CONCEPT_HDL CORE Schematic page import causes re-sectioning of the pins.
1326163 SIP_LAYOUT OTHER SiP Layout - Void Adjacent Layer - Include option to ignore same net object when voiding
1326696 CONCEPT_HDL CORE Cannot get concepthdl -product to invoke with the high speed already available
1327367 CONCEPT_HDL CORE Crash when saving after adding block pin
1327569 ADW LRM LRM does not update the headers if the part number is also changed
1329271 ALLEGRO_EDITOR DRC_CONSTR Multithreading DRC check is flagging a DRC on the TOP Layer for Route Keepout that has the property
1329587 CONCEPT_HDL CORE Using the GROUP command does NOT place all objects in the group back on grid
1330913 CONCEPT_HDL COMP_BROWSER Empty value in PTF file
1332728 SIG_INTEGRITY OTHER Signal model assignment form returning SYNTAX ERROR on Linux 5.0 5.7 and 5.9 with hotfix s036 and s037.
CCRID PRODUCT PRODUCTLEVEL2 TITLE
=========================================================================================
1103937 PCB_LIBRARIAN VERIFICATION con2con should not have any need for a graphical terminal
1107843 FSP OTHER Support for lrf and lmf in archived project
1123765 CAPTURE GENERAL .OLBlck file not deleted if library is closed in Capture
1169740 FSP OTHER Ability to import "Assigned Pin" column to connect Generic connector and FPGA.
1172641 FSP FPGA_SUPPORT Support for 5SGSMD5K2F40I2N device
1177760 CAPTURE OTHER IC pins cannot be cross probed from Capture to PCB Editor
1195672 ALLEGRO_EDITOR PLACEMENT Place replicate update should update component value text
1206563 FSP GUI Spreadsheet import support for xc3s400afg400
1208169 FSP FPGA_SUPPORT New FPGA model request
1224428 ALLEGRO_EDITOR PLACEMENT Get message "W-(SPMHGE-579): Unable to complete path to circuit for all selections" when updating place replicate circuit
1230064 ALLEGRO_EDITOR INTERACTIV Place replicate is trying to match dimensions
1253986 CONCEPT_HDL CORE Not able to define Source when adding property to a selected group
1266615 ADW SHOPINGCART Error(SPDWUB-48) while placing the part from the shopping cart
1269658 ALLEGRO_EDITOR EDIT_ETCH Ratsnest disappears near pin when routing
1270158 CONCEPT_HDL CONSTRAINT_MGR Orphan nets are visible in CM but not in DE-HDL
1275042 CONCEPT_HDL COMP_BROWSER Unit specifier 'HC' not found in UNITS environment while placing the part on schematic
1276269 ALLEGRO_EDITOR TESTPREP On creating a fixture, a test point is generated but refs are not visible.
1278037 SIP_LAYOUT ASSY_RULE_CHECK DRC soldermask to finger check required for cases when the finger has no wire attached
1278475 ALLEGRO_EDITOR DATABASE Import Logic changes VIA net names to GND
1279162 SIP_LAYOUT DIE_ABSTRACT_IF Add codesign die should default shrink/scribe settings from die abstract if abstract contains this information.
1282358 SIP_LAYOUT OTHER Why are IC/PKG symbols always mirrored when placed on a sip design?
1283439 CAPTURE ANNOTATE Inter Sheet Refs placed on top of Off Page Connector name
1284809 ALLEGRO_EDITOR INTERACTIV Using the Fix icon in the toolbar will not apply the Fixed property to Groups
1286277 CAPTURE SCHEMATICS Capture crashes on adding Bezier curves
1286354 CONCEPT_HDL CORE The GENERATE_SCH_METADATA 'ON' directive causes significant DE-HDL performance degradation
1286617 CONCEPT_HDL CORE Generate View failure
1287020 CAPTURE OTHER Option to disable Autobackup
1287100 FSP DESIGN_SETTINGS FSP global edit of Capture library paths
1287877 CONCEPT_HDL CHECKPLUS Graphic check in CheckPlus hangs with sch_something view
1289056 ADW OTHER MKnet program to also read the alim.auto from ADW_CONF_ROOT
1289107 CONCEPT_HDL CORE Find with Schematic Selection fails after clicking Find All three times
1289175 CAPTURE OPTIONS Autobackup changes timestamp of each and every part in the library.
1289447 TDA CORE Undo Check-out removes new design data from local area
1289677 ALLEGRO_EDITOR SHAPE Complex shape filling fails without DRC
1289755 ALLEGRO_EDITOR EDIT_ETCH Timing Vision Display error
1289913 ALLEGRO_EDITOR EDIT_ETCH Enhance the fanout function to speed up the layout design in Allegro PCB Editor.
1290136 ALLEGRO_EDITOR EDIT_ETCH Unable to connect IC pin to ground
1290426 SIP_LAYOUT LOGIC Deleting a distributed codesign component from parts list does not remove the component information from the design database
1291888 ALLEGRO_EDITOR INTERACTIV Property DYN_DELETED_ISLAND is not added on all the voids created by Delete Island command
1292206 ALLEGRO_EDITOR OTHER Allow netname to be visible for pin/cline when viewed in Allegro PDF Publisher
1292234 APD SHAPE Shape does not Void around Clines and Vias due to some corruption
1292877 ALLEGRO_EDITOR DATABASE DB doctor fixed void boundary but deleted all boundary without detail information.
1293041 ADW COMPONENT_BROWSE Component Browser does not show results if you filter on the PPL and an additional column
1293188 ALLEGRO_EDITOR EDIT_ETCH fanout function(via in pad) deleted the cline & thermal
1293626 CONCEPT_HDL CORE Delete Page command could not delete the dependency file (page2.csd).
1293710 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during copy fanout
1294355 PSPICE SIMULATOR Function "ddt( )" behavior in DC sweep analysis
1295232 CAPTURE SCHEMATIC_EDITOR Remove from group changes not reflected consistently in Part Manager
1295434 ALLEGRO_EDITOR INTERACTIV Enable Pin Name to be imported into a .BRD and display this in the show info output as done in APD and SIP
1296583 ALLEGRO_EDITOR FSP_PINSWAP Crash for FSP Auto Pinswap with PCB Editor
1297095 ADW LRM LRM replaces incorrect part in schematic.
1297685 F2B DESIGNVARI 'Could not open xmodules.dat file' Error during 'Save'.
1297835 ALLEGRO_EDITOR INTERACTIV DFA-Driven Interactive Placement not working correctly for components on bottom side
1297870 SIP_LAYOUT ASSY_RULE_CHECK Wire to Wire Optical short ADRC reports wrong DRC violation
1297994 ALLEGRO_EDITOR INTERACTIV When moving a via and splitting the stack, the via moves off the design work surface.
1298129 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Phase tuning should have option to Allow DRCs
1299050 ADW PCBCACHE Need a way to turn off all project ptf file backup files under flatlib
1299873 CONCEPT_HDL CORE DE-HDL window size and position is not saved on exit
1300101 ALLEGRO_EDITOR GRAPHICS Inconsistency in symbol editor and PCB Editor while showing 3D view
1300557 ALLEGRO_EDITOR EDIT_ETCH Move Component with "Slide Etch" or "Stretch Etch" removes DYN_CLEARANCE_OVERSIZE from clines
1300806 ALLEGRO_EDITOR GRAPHICS Stroke command in 16.6 works differently as compared with earlier versions
1302103 CONCEPT_HDL CONSTRAINT_MGR DE-HDL CM startup time on large hierarchical is extremely large(6-8 min)
1302939 ALLEGRO_EDITOR PARTITION Place replicate modules lost with design partition
1303078 CAPTURE STABILITY Capture crashes on View – Status Bar with no design open
1303106 ALLEGRO_EDITOR SKILL Creating shape with SKILL script does not work on SPB16.5 and SPB16.6.
1303442 ALLEGRO_EDITOR EDIT_ETCH auto-interactive convert corner function crashes PCB Editor
1303921 ADW COMPONENT_BROWSE Datasheets with spaces are not viewable in component browser
1304042 APD LOGIC ERROR(SPMHUT-43):netin command is not working for .mcm.
1304725 ALLEGRO_EDITOR INTERACTIV Value 0 in Allegro Text Setup not valid anymore
1304734 ALLEGRO_EDITOR PADS_IN PADS_IN does not follow the settings in the options file
1304882 CONCEPT_HDL CORE Hierarchy Viewer jumps up to the top on File Save
1305147 ALLEGRO_EDITOR MANUFACT Auto silk result is unstable.
1306323 ALLEGRO_EDITOR INTERACTIV Mirror command does not seem to work correctly.
1306468 ALLEGRO_EDITOR DATABASE Dbdoctor Crash
1307277 SIP_LAYOUT IMPORT_DATA Wants BGA Text-In Wizard to maintain Pad layer set in the text file instead of defaulting to Bottom layer.
1307367 FSP FPGA_SUPPORT FSP user needs 5SGSMD5K3F40I3N/5SGSED6K3F40I3N in FPGA models.
1307478 ALLEGRO_EDITOR MENTOR unable to do PADS Library translation.
1307626 ALLEGRO_EDITOR INTERACTIV Pick window is different for command and from GUI
1307785 ASI_PI GUI Decap Configuration GUI does not update until you deselect then select GND
1308163 SIP_LAYOUT ORBITIO_IF Importing OrbitIO with multiple packages and XDA file into SIP layout results in incomplete data
1308289 SIP_LAYOUT ORBITIO_IF Import OrbitIO into existing SIP database fails. Testing an ECO type of design flow
1309315 CAPTURE ANNOTATE Incremental annotation is not giving correct refdes in case of attached complex hierarchical design
1310614 CONCEPT_HDL CORE Part Manager creates bogus directory on linux system
1311184 CAPTURE NETLIST_ALLEGRO Incorrect warning for DEVICE property value in netlisting.
1311719 ALLEGRO_EDITOR INTERACTIV Allegro Component will not place on the canvas
1311757 CONCEPT_HDL CORE Cannot change a property from instance level to non-instance level
1311848 CONSTRAINT_MGR OTHER PFE is adding a capacitor after creating PI CSet
1312553 CONCEPT_HDL CORE Customer could not add their net property after deleting it.
1313068 APD DIE_ESCAPE die escape gen: Cannot route from pad of Via Structure.
1313239 CONSTRAINT_MGR CONCEPT_HDL Diff pair constraints disappear if xnet is created for them in Editor
1313850 ALLEGRO_EDITOR PLACEMENT Place Replicate ignores fillet at pins
1314207 ALLEGRO_EDITOR OTHER PCB Editor crash when rotating IPF data
1314467 ALLEGRO_EDITOR INTERACTIV With high_speed option selected, PCB Editor crashes on move operation
1314921 ALLEGRO_EDITOR PLACEMENT RATS are wrongly displayed.
1314973 CAPTURE OTHER Cannot cross-probe all pins from Capture
1316295 ALLEGRO_EDITOR OTHER .brd extension is removed after running DB Doctor from PCB Editor Utilities.
1316757 ALLEGRO_EDITOR DRC_CONSTR Spacing constraint error on negative layer
1316959 ALLEGRO_EDITOR PARTITION Exported soft boundary partition2 symbol still cannot move out of partition boundary
1317157 SIP_LAYOUT DIE_STACK_EDITOR After moving the Dies to different layers a Wirebond has changed the connection from the pin to a shape.
1317480 ALLEGRO_EDITOR SYMBOL Allegro DB check "SPMHA1-247 Illegal mirror error"
1317614 ADW COMPONENT_BROWSE Datasheet_Url is not opening the file browser correctly
1317876 APD COLOR APD crashes when executing Color Dialog for Nets
1320028 FSP DE-HDL_SCHEMATIC Error (10002: Cannot find a ppt part that matches the instance properties
1320438 ALLEGRO_EDITOR GRAPHICS Could not save DFA spreadsheet
1322600 CONCEPT_HDL CONSTRAINT_MGR Cannot extract xnet topology due to missing model even if the model is present
1323327 CONCEPT_HDL CONSTRAINT_MGR Deleting Ref Electrical CSet from Diff Pair removes it from a Matched Group in DE-HDL
1325230 CONCEPT_HDL CORE DE-HDL crashes once the design is loaded.
1325644 F2B PACKAGERXL CDS_LOCATION/$PN not deleted from property file(dcf) backannotation warnings
1325905 CONCEPT_HDL CORE Schematic page import causes re-sectioning of the pins.
1326163 SIP_LAYOUT OTHER SiP Layout - Void Adjacent Layer - Include option to ignore same net object when voiding
1326696 CONCEPT_HDL CORE Cannot get concepthdl -product to invoke with the high speed already available
1327367 CONCEPT_HDL CORE Crash when saving after adding block pin
1327569 ADW LRM LRM does not update the headers if the part number is also changed
1329271 ALLEGRO_EDITOR DRC_CONSTR Multithreading DRC check is flagging a DRC on the TOP Layer for Route Keepout that has the property
1329587 CONCEPT_HDL CORE Using the GROUP command does NOT place all objects in the group back on grid
1330913 CONCEPT_HDL COMP_BROWSER Empty value in PTF file
1332728 SIG_INTEGRITY OTHER Signal model assignment form returning SYNTAX ERROR on Linux 5.0 5.7 and 5.9 with hotfix s036 and s037.
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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Name: Cadence SPB OrCAD
Version: (32bit) 16.60.038 Hotfix
Home: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.037
Size: 1.1 Gb
Special Thanks 0mBrE
Cadence SPB OrCAD 16.60.038 Hotfix
visit my blog
All parts on filepost.com, rapidgator.com, nitroflare.com interchanged. It is added by 5% of the overall size of the archive of information for the restoration and the volume for the restoration
No mirrors please