Cadence SPB OrCAD 16.60.037 Hotfix | 1.0 Gb
Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released an hotfix 37 for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1314031 CONCEPT_HDL CORE GenView should automatically refresh the page where the block symbol has been instantiated
1318575 SIG_EXPLORER SIMULATION Display Parasitic on Wirebond (selecting the second one) crashes APD
1319258 ALLEGRO_EDITOR INTERFACES Enhance IPC-2581 so that the rotation of pad shapes is defined at the LandPattern definition and Pin elements levels
1320054 ALLEGRO_EDITOR INTERFACES IPC2581 Import Stackup
1320467 CONCEPT_HDL CORE Incorrect directives in cds.cpm for nconcepthdl (cont.)
1320878 ALLEGRO_EDITOR EDIT_ETCH Allegro crash when using scribble
1321319 ALLEGRO_EDITOR INTERFACES Step Export has wrong size
1322394 CONCEPT_HDL OTHER Packager runs without errors even when the DEHDL schematic pages are corrupt.
1323892 CONCEPT_HDL CORE The SI_MODEL_PATH should not write to $HOME/pcbenv/env
1324438 SIP_LAYOUT EXPORT_DATA SiP Layout - netlist spreadsheet, Error on exporting a spreadsheet on design file
1324533 F2B PACKAGERXL Export Physical fails - pxl.exe has stopped working
CCRID PRODUCT PRODUCTLEVEL2 TITLE
==========================================================================================================
1314031 CONCEPT_HDL CORE GenView should automatically refresh the page where the block symbol has been instantiated
1318575 SIG_EXPLORER SIMULATION Display Parasitic on Wirebond (selecting the second one) crashes APD
1319258 ALLEGRO_EDITOR INTERFACES Enhance IPC-2581 so that the rotation of pad shapes is defined at the LandPattern definition and Pin elements levels
1320054 ALLEGRO_EDITOR INTERFACES IPC2581 Import Stackup
1320467 CONCEPT_HDL CORE Incorrect directives in cds.cpm for nconcepthdl (cont.)
1320878 ALLEGRO_EDITOR EDIT_ETCH Allegro crash when using scribble
1321319 ALLEGRO_EDITOR INTERFACES Step Export has wrong size
1322394 CONCEPT_HDL OTHER Packager runs without errors even when the DEHDL schematic pages are corrupt.
1323892 CONCEPT_HDL CORE The SI_MODEL_PATH should not write to $HOME/pcbenv/env
1324438 SIP_LAYOUT EXPORT_DATA SiP Layout - netlist spreadsheet, Error on exporting a spreadsheet on design file
1324533 F2B PACKAGERXL Export Physical fails - pxl.exe has stopped working
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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Name: Cadence SPB OrCAD
Version: (32bit) 16.60.037 Hotfix
Home: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.036
Size: 1.0 Gb
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