Cadence SPB OrCAD 16.5.026 (Allegro SPB) Hotfix
Cadence SPB OrCAD 16.5.026 (Allegro SPB) Hotfix | 654.4 mb
Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.
To stay competitive in today’s market, companies must move their designs from engineering to manufacturing within ever-shrinking design schedules. Available as standalone products or in comprehensive suites, Cadence OrCAD personal productivity tools have a long history of addressing PCB design challenges, whether simple or complex. The powerful, tightly integrated PCB design technologies include OrCAD Capture for schematic design, various librarian tools, OrCAD PCB Editor for place and route, PSpice A/D for circuit simulation, OrCAD PCB SI for signal integrity analysis, and SPECCTRA for OrCAD for automatic routing. Easy to use and intuitive, these tools bring exceptional value and future-proof scalability to the Cadence Allegro system interconnect design platform to grow with future design demands. OrCAD PCB design suites provide integrated front-end design and simulation technology (Cadence OrCAD EE Designer) as well as an integrated back-end place-and-route design solution (Cadence OrCAD PCB Designer) to boost productivity and accelerate time to market.
DATE: 07-27-2012 HOTFIX VERSION: 026
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
841657 FSP DE-HDL_SCHEMATIC All ports of virtual interfaces are inout in schematic regardless of VI definitions.
868380 FSP ALLEGRO_INTEGRAT improve error message Invalid design database encountered for ECO mode. Collaboration data was found for the following d
904790 SCM OTHER Update the format of the time displayed in the session log
904794 SCM OTHER Enhance the time displayed in the verilog file to support DST
920740 CONCEPT_HDL CORE Detailed info about syntax error while executing "publishpdf" from Command Line.
921934 CONCEPT_HDL CORE Clicking on Next page command would take you to the beginning of the schematic (page1)
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
927609 CONCEPT_HDL OTHER CREF links bounded by rectangular box in generated PDF
957030 CAPTURE DRC DRC warning message for net group is not correct
957723 CONCEPT_HDL CAEVIEWS Customer can not get DIFFERENTIAL_PAIR properties by CAEViews.
957913 CONCEPT_HDL CORE Segmentation fault when running DE HDL from a command line with a script
966191 SIG_INTEGRITY OTHER Xnets to be split didn't work correctly.
970597 CONCEPT_HDL INFRA 16.5 schematic uprev fails if lib parts are missing
974361 ALLEGRO_EDITOR EDIT_ETCH Difference in length between Show Element and CM when Z-Axis delay is enabled.
975531 CAPTURE NETLIST_ALLEGRO Error initializing COM property pages: Invalid pointer even after trying solution 11698280
977375 CONCEPT_HDL CORE Unable to open the same Page of Base Schematic along with CRef Schematic Page.
981219 CONCEPT_HDL CORE PaperSize A1 is not correctly managed by wplot_paper
981613 SCM SCHGEN ASA Schegen fails/crash on specific block in ASA design
981744 SCM SCHGEN schgen does not preserve connectivity and property related changes when done together
981809 SCM OTHER ASA does handle PACK_SHORT pins
982004 ALLEGRO_EDITOR GRAPHICS Allegro crash when viewing and zoom in for subclass
989083 PCB_LIBRARIAN CORE PDV shows converted scalar to vector pins on symbol as Q_N<2..0> and in symbol pins as Q<2..0>_N
989518 CONCEPT_HDL CORE DEHDL crash with Search Result tab
990582 FSP NET_EDITING Method to support the net names in the design to be driven by the FPGA port name
994504 PCB_LIBRARIAN CORE PDV adding text should respect the snap to grid grid settings and text justification
995351 ALLEGRO_EDITOR EDIT_ETCH Enhance Allegro 16.5's slide with Vertex Action function of new Slide in SPB 16.6
996019 PCB_LIBRARIAN CORE PDV having text on 2 lines having CR/LF is lost when reloading the symbol
998499 CONCEPT_HDL CORE Attributes sticks to the component when its copied
998987 FSP DESIGN_SETTINGS Hyphen in project name should not be allowed while creating new project itself.
1000604 FSP DE-HDL_SCHEMATIC Component ripping off from the board after second pass of Schgen
1001563 FSP SCRIPTING_INTERF TCL command to dump the path to rules file and mapping file used by every part in a FSP project
1002462 CONCEPT_HDL CORE Block Stretch disrupts pins
1003110 PCB_LIBRARIAN AUTOMATION PDV Symbol Property Outline Offset value zero wrong interpreted as -200
1003253 CAPTURE PROPERTY_EDITOR property is not removed from Browse Spreadsheet in H design
1004093 CONCEPT_HDL OTHER Disable Default setting in Product Choice for Project manager
1004249 CONCEPT_HDL CORE DEHDL global search crashes on a ? search
1005890 PSPICE PROBE Probe Window crashes when &P is added in the Probe Page Header
1006183 CIS FOOTPRINT_VIEW Incorrect pin details in 3D Footprint Viewer.
1006336 SIG_EXPLORER OTHER diif pair nets with shape traces cannot be extracted into sigxp
1006862 CONCEPT_HDL INFRA Uprev process is tedious and requires lot of manual effort for a design with multiple reuse blocks
1007198 CONCEPT_HDL INFRA Room property getting the wrong value after packaging an upreved design
1007732 CAPTURE NETLIST_OTHER Q: Why does wirelist netlist adds an extra NODE for some connections made using POWER GROUP?
1007781 CONCEPT_HDL OTHER Generated pdf for design upreved from 16.3 has occ_only attributes
1007995 FSP DE-HDL_SCHEMATIC FSP schematic generation needs abiltiy to pick power symbols just like ASA
1008112 FSP DE-HDL_SCHEMATIC port directions set inside FSP need to be used for ports in schgen
1008507 PCB_LIBRARIAN OTHER Base Part Developer isnїt there with the PCB Designer license of 1650.
1009001 CONCEPT_HDL OTHER Graphics Color setting form is strange on Win7.
1009077 CONCEPT_HDL CORE unable to uprev the design
1009109 SIG_INTEGRITY OTHER User defined diff pair pin pairs are mixed in match group
1010569 CONCEPT_HDL OTHER Sort Old Signal Name column in paste special
1010661 PCB_LIBRARIAN CORE Save as the part with different in PDV changes all the property values
1011424 CONCEPT_HDL CREFER Component attributes are set to invisible in the flatten schematics generated from CRefer
1011431 FSP PROCESS Incorrect selection of protocols under їProcess Optionsї window
1011474 FSP OTHER Easier way to read lengthier message which comes in no connect report (Report for Signals).
1011525 PCB_LIBRARIAN CORE the reload does not update sym_1 immediately
1011618 SIP_LAYOUT DIE_ABSTRACT_IF Add Co-design die from DIA should add any missing non-conductor subclasses for import of package shapes.
1011629 CONCEPT_HDL INFRA RefDes change on schematic after upreving from SPB 16.3 to 16.5
1012750 CONCEPT_HDL ARCHIVER The SI_MODEL_PATH from ARCHIVE_SI_MODEL_FILES directive of Archiver
1012942 CAPTURE SCHEMATICS ORCAD V16.5 open Capture DOS SDT Schematic issue
1013377 ALLEGRO_EDITOR DRAFTING Allow edit and delete vertex in dimension environment
1013795 ALLEGRO_EDITOR MANUFACT Tolerance value for Angular Dimension using "Plus or Minus" type is not working correctly in new Dimesnion environment
1014142 CONCEPT_HDL CORE Customer have dump file when they run Script on DE-HDL16.5
1014243 CONSTRAINT_MGR CONCEPT_HDL Default setting of Constraint Manager's Filter.
1014334 CONCEPT_HDL INFRA Incorrect refdes and source after first Export Physical.
1014853 CAPTURE NETGROUPS Error (ORCAP-1839) Invalid Character in Netgroup name (minus sign)
1015256 ALLEGRO_EDITOR OTHER Allegro Crash while working with Dimensioning Environment
1015397 SIP_LAYOUT DIE_ABSTRACT_IF Support bumps provided in die abstract in hierarchical blocks
1016859 SCM REPORTS dsreportgen exits with %errorlevel%
1016891 APD VIA_STRUCTURE Log file does not indicate the problem or how to fix when refreshing Via Stuctures fails.
1017173 ALLEGRO_EDITOR GRAPHICS moving a via changes it's size to the NC figure
1017337 CONCEPT_HDL OTHER DEHDL Recover adds extra page border
1018348 SCM SCHGEN Generate schematic hangs when creating pages
1019977 CONCEPT_HDL CORE Upver changes voltage property value
1020163 CONCEPT_HDL CREFER missing page after running CREFER in schcref of flat design
1021620 ALLEGRO_EDITOR OTHER LINUX UNIX (AIX) numlock maps incorrectly
1021869 PCB_LIBRARIAN CORE SCM should not crash when using the attached design.
1022117 PCB_LIBRARIAN CORE Warning(SPCODD-44): File xxx/fsp.ptf not found
1023715 CONCEPT_HDL OTHER After runnign genview dashboard does not show the sym_1 view as being modified.
1025482 CONCEPT_HDL INFRA dcf file not getting updated
1026153 CONCEPT_HDL CORE DE HDL crashes while saving.
1028240 F2B PACKAGERXL plx.exe has stopped working plx.log is empty
1029213 ALLEGRO_EDITOR SHOW_ELEM Allegro crashes on Show Element when showelement_highspeed is set.
1029217 SCM SCHGEN Schgen creates schematics with no visable netnames.
1029596 ALLEGRO_EDITOR PADS_IN PADS_IN dropping net name on few pins
1029606 SIP_LAYOUT MODULES The place manually crashes the application
1030385 ALLEGRO_EDITOR INTERFACES Import DXF fails to import text and flag note symbols correctly
1031255 SCM UI SCM Replace Component form will not sort the columns.
1031324 ALLEGRO_EDITOR EDIT_ETCH Double click to add via crashes allegro
1031676 ALLEGRO_EDITOR OTHER Auto Rename Refdes Crashes Allegro
1033291 CONCEPT_HDL INFRA DE-HDL crashes if Search is started while the design is loading
1034699 CONSTRAINT_MGR OTHER Constraint Manager Update DRC deletes waived DRC's comments.
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
841657 FSP DE-HDL_SCHEMATIC All ports of virtual interfaces are inout in schematic regardless of VI definitions.
868380 FSP ALLEGRO_INTEGRAT improve error message Invalid design database encountered for ECO mode. Collaboration data was found for the following d
904790 SCM OTHER Update the format of the time displayed in the session log
904794 SCM OTHER Enhance the time displayed in the verilog file to support DST
920740 CONCEPT_HDL CORE Detailed info about syntax error while executing "publishpdf" from Command Line.
921934 CONCEPT_HDL CORE Clicking on Next page command would take you to the beginning of the schematic (page1)
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
927609 CONCEPT_HDL OTHER CREF links bounded by rectangular box in generated PDF
957030 CAPTURE DRC DRC warning message for net group is not correct
957723 CONCEPT_HDL CAEVIEWS Customer can not get DIFFERENTIAL_PAIR properties by CAEViews.
957913 CONCEPT_HDL CORE Segmentation fault when running DE HDL from a command line with a script
966191 SIG_INTEGRITY OTHER Xnets to be split didn't work correctly.
970597 CONCEPT_HDL INFRA 16.5 schematic uprev fails if lib parts are missing
974361 ALLEGRO_EDITOR EDIT_ETCH Difference in length between Show Element and CM when Z-Axis delay is enabled.
975531 CAPTURE NETLIST_ALLEGRO Error initializing COM property pages: Invalid pointer even after trying solution 11698280
977375 CONCEPT_HDL CORE Unable to open the same Page of Base Schematic along with CRef Schematic Page.
981219 CONCEPT_HDL CORE PaperSize A1 is not correctly managed by wplot_paper
981613 SCM SCHGEN ASA Schegen fails/crash on specific block in ASA design
981744 SCM SCHGEN schgen does not preserve connectivity and property related changes when done together
981809 SCM OTHER ASA does handle PACK_SHORT pins
982004 ALLEGRO_EDITOR GRAPHICS Allegro crash when viewing and zoom in for subclass
989083 PCB_LIBRARIAN CORE PDV shows converted scalar to vector pins on symbol as Q_N<2..0> and in symbol pins as Q<2..0>_N
989518 CONCEPT_HDL CORE DEHDL crash with Search Result tab
990582 FSP NET_EDITING Method to support the net names in the design to be driven by the FPGA port name
994504 PCB_LIBRARIAN CORE PDV adding text should respect the snap to grid grid settings and text justification
995351 ALLEGRO_EDITOR EDIT_ETCH Enhance Allegro 16.5's slide with Vertex Action function of new Slide in SPB 16.6
996019 PCB_LIBRARIAN CORE PDV having text on 2 lines having CR/LF is lost when reloading the symbol
998499 CONCEPT_HDL CORE Attributes sticks to the component when its copied
998987 FSP DESIGN_SETTINGS Hyphen in project name should not be allowed while creating new project itself.
1000604 FSP DE-HDL_SCHEMATIC Component ripping off from the board after second pass of Schgen
1001563 FSP SCRIPTING_INTERF TCL command to dump the path to rules file and mapping file used by every part in a FSP project
1002462 CONCEPT_HDL CORE Block Stretch disrupts pins
1003110 PCB_LIBRARIAN AUTOMATION PDV Symbol Property Outline Offset value zero wrong interpreted as -200
1003253 CAPTURE PROPERTY_EDITOR property is not removed from Browse Spreadsheet in H design
1004093 CONCEPT_HDL OTHER Disable Default setting in Product Choice for Project manager
1004249 CONCEPT_HDL CORE DEHDL global search crashes on a ? search
1005890 PSPICE PROBE Probe Window crashes when &P is added in the Probe Page Header
1006183 CIS FOOTPRINT_VIEW Incorrect pin details in 3D Footprint Viewer.
1006336 SIG_EXPLORER OTHER diif pair nets with shape traces cannot be extracted into sigxp
1006862 CONCEPT_HDL INFRA Uprev process is tedious and requires lot of manual effort for a design with multiple reuse blocks
1007198 CONCEPT_HDL INFRA Room property getting the wrong value after packaging an upreved design
1007732 CAPTURE NETLIST_OTHER Q: Why does wirelist netlist adds an extra NODE for some connections made using POWER GROUP?
1007781 CONCEPT_HDL OTHER Generated pdf for design upreved from 16.3 has occ_only attributes
1007995 FSP DE-HDL_SCHEMATIC FSP schematic generation needs abiltiy to pick power symbols just like ASA
1008112 FSP DE-HDL_SCHEMATIC port directions set inside FSP need to be used for ports in schgen
1008507 PCB_LIBRARIAN OTHER Base Part Developer isnїt there with the PCB Designer license of 1650.
1009001 CONCEPT_HDL OTHER Graphics Color setting form is strange on Win7.
1009077 CONCEPT_HDL CORE unable to uprev the design
1009109 SIG_INTEGRITY OTHER User defined diff pair pin pairs are mixed in match group
1010569 CONCEPT_HDL OTHER Sort Old Signal Name column in paste special
1010661 PCB_LIBRARIAN CORE Save as the part with different in PDV changes all the property values
1011424 CONCEPT_HDL CREFER Component attributes are set to invisible in the flatten schematics generated from CRefer
1011431 FSP PROCESS Incorrect selection of protocols under їProcess Optionsї window
1011474 FSP OTHER Easier way to read lengthier message which comes in no connect report (Report for Signals).
1011525 PCB_LIBRARIAN CORE the reload does not update sym_1 immediately
1011618 SIP_LAYOUT DIE_ABSTRACT_IF Add Co-design die from DIA should add any missing non-conductor subclasses for import of package shapes.
1011629 CONCEPT_HDL INFRA RefDes change on schematic after upreving from SPB 16.3 to 16.5
1012750 CONCEPT_HDL ARCHIVER The SI_MODEL_PATH from ARCHIVE_SI_MODEL_FILES directive of Archiver
1012942 CAPTURE SCHEMATICS ORCAD V16.5 open Capture DOS SDT Schematic issue
1013377 ALLEGRO_EDITOR DRAFTING Allow edit and delete vertex in dimension environment
1013795 ALLEGRO_EDITOR MANUFACT Tolerance value for Angular Dimension using "Plus or Minus" type is not working correctly in new Dimesnion environment
1014142 CONCEPT_HDL CORE Customer have dump file when they run Script on DE-HDL16.5
1014243 CONSTRAINT_MGR CONCEPT_HDL Default setting of Constraint Manager's Filter.
1014334 CONCEPT_HDL INFRA Incorrect refdes and source after first Export Physical.
1014853 CAPTURE NETGROUPS Error (ORCAP-1839) Invalid Character in Netgroup name (minus sign)
1015256 ALLEGRO_EDITOR OTHER Allegro Crash while working with Dimensioning Environment
1015397 SIP_LAYOUT DIE_ABSTRACT_IF Support bumps provided in die abstract in hierarchical blocks
1016859 SCM REPORTS dsreportgen exits with %errorlevel%
1016891 APD VIA_STRUCTURE Log file does not indicate the problem or how to fix when refreshing Via Stuctures fails.
1017173 ALLEGRO_EDITOR GRAPHICS moving a via changes it's size to the NC figure
1017337 CONCEPT_HDL OTHER DEHDL Recover adds extra page border
1018348 SCM SCHGEN Generate schematic hangs when creating pages
1019977 CONCEPT_HDL CORE Upver changes voltage property value
1020163 CONCEPT_HDL CREFER missing page after running CREFER in schcref of flat design
1021620 ALLEGRO_EDITOR OTHER LINUX UNIX (AIX) numlock maps incorrectly
1021869 PCB_LIBRARIAN CORE SCM should not crash when using the attached design.
1022117 PCB_LIBRARIAN CORE Warning(SPCODD-44): File xxx/fsp.ptf not found
1023715 CONCEPT_HDL OTHER After runnign genview dashboard does not show the sym_1 view as being modified.
1025482 CONCEPT_HDL INFRA dcf file not getting updated
1026153 CONCEPT_HDL CORE DE HDL crashes while saving.
1028240 F2B PACKAGERXL plx.exe has stopped working plx.log is empty
1029213 ALLEGRO_EDITOR SHOW_ELEM Allegro crashes on Show Element when showelement_highspeed is set.
1029217 SCM SCHGEN Schgen creates schematics with no visable netnames.
1029596 ALLEGRO_EDITOR PADS_IN PADS_IN dropping net name on few pins
1029606 SIP_LAYOUT MODULES The place manually crashes the application
1030385 ALLEGRO_EDITOR INTERFACES Import DXF fails to import text and flag note symbols correctly
1031255 SCM UI SCM Replace Component form will not sort the columns.
1031324 ALLEGRO_EDITOR EDIT_ETCH Double click to add via crashes allegro
1031676 ALLEGRO_EDITOR OTHER Auto Rename Refdes Crashes Allegro
1033291 CONCEPT_HDL INFRA DE-HDL crashes if Search is started while the design is loading
1034699 CONSTRAINT_MGR OTHER Constraint Manager Update DRC deletes waived DRC's comments.
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Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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Name: Cadence SPB OrCAD
Version: 16.5.026 (Allegro SPB) 32bit Hotfix
Creator: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB/OrCAD 16.50.000 - 16.50.025
OS: Windows XP / Vista / Seven
Size: 654.4 mb
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