Cadence SPB OrCAD 16.5.0(11)13 (Allegro SPB) Hotfix
Cadence SPB OrCAD 16.5.0(11)13 (Allegro SPB) Hotfix | 1.0 Gb
Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.
Company Profile
To keep pace with market demand for more performance and functionality in today’s mobile phones, digital cameras, computers, automotive systems and other electronics products, manufacturers pack billions of transistors onto a single chip. This massive integration parallels the shift to ever-smaller process geometries, where the chip’s transistors and other physical features can be smaller than the wavelength of light used to print them.
Designing and manufacturing semiconductor devices with such phenomenal scale, complexity and technological challenges would not be possible without electronic design automation (EDA). It is essential for everything from verifying that the myriad transistors do what the designer intended to dealing with physical effects on electrons traveling miles of wires with widths sometimes measuring less than 100 nanometers.
Cadence Design Systems is the world's leading EDA company. Cadence customers use our software, hardware, and services to overcome a range of technical and economic hurdles.
New Allegro 16.5 Technology
The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as:
- Higher functional density with a constraint-driven flow for embedded components
- Faster timing closure with new PCB interconnect design planning technology
- Fewer physical prototype iterations with concurrent team design authoring
- More efficient low-power design with integrated power delivery network analysis
- A compliant and faster implementation path with package/board-aware SoC IP
- Smoother collaboration among global teams with new SiP distributed co-design
- Flexibility through “base plus options” configurations
DATE: 12-16-2011 HOTFIX VERSION: 013
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
946770 CONCEPT_HDL CORE “View Design” function is missing in Windows Mode after reseting the menus.
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "“separate files for plated/nonplatedholes”
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
954498 SCM B2F SCM crashes when importing physical
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
957137 APD DXF_IF DXF out command dose not work correctly.
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
957267 CONCEPT_HDL INFRA Packager Error after Import Design
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
959253 CONCEPT_HDL INFRA Design will not open
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
DATE: 11-30-2011 HOTFIX VERSION: 012
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats
DATE: HOTFIX VERSION: 011
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
937165 SCM SCHGEN Can't generate Schematic
937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
946350 F2B DESIGNVARI Variant Editor rename function removes all components
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form
946458 SCM SCHGEN Schematic generator adding an unnecessary page
947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
952057 SCM PACKAGER Export Physical does not works correctly from SCM
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
953018 APD REPORTS Shape affects Package Report result.
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
953918 GRE CORE GRE cannot route second and third row of pad in die symbol.
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
946770 CONCEPT_HDL CORE “View Design” function is missing in Windows Mode after reseting the menus.
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "“separate files for plated/nonplatedholes”
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
954498 SCM B2F SCM crashes when importing physical
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
957137 APD DXF_IF DXF out command dose not work correctly.
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
957267 CONCEPT_HDL INFRA Packager Error after Import Design
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
959253 CONCEPT_HDL INFRA Design will not open
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
DATE: 11-30-2011 HOTFIX VERSION: 012
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats
DATE: HOTFIX VERSION: 011
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
937165 SCM SCHGEN Can't generate Schematic
937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
946350 F2B DESIGNVARI Variant Editor rename function removes all components
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form
946458 SCM SCHGEN Schematic generator adding an unnecessary page
947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
952057 SCM PACKAGER Export Physical does not works correctly from SCM
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
953018 APD REPORTS Shape affects Package Report result.
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
953918 GRE CORE GRE cannot route second and third row of pad in die symbol.
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
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Name: Cadence SPB OrCAD
Version: 16.5.00(11)13 (Allegro SPB) 32bit Hotfix
Creator: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
Platform: Cadence SPB/OrCAD 16.5.000
OS: Windows XP / Vista / Seven
Size: 1.0 Gb
Note: To install the latest update, do not install anything just download and install the latest. But in previous versions of SPB happened that after the upgrade appear 'fresh' glitches, then try the previous one.
Cadence SPB OrCAD 16.5.009 (Allegro SPB) Hotfix
Cadence SPB OrCAD 16.5.008 (Allegro SPB) Hotfix
Cadence SPB OrCAD 16.5.00(5,6)7(Allegro SPB) Hotfix
Cadence SPB OrCAD 16.5.00(1,2) (Allegro SPB) Hotfix
Cadence SPB/OrCAD 16.5.000 (Allegro SPB)
All parts on filepost.com, fileserve.com, filesonic.com interchanged. It is added by 5% of the overall size of the archive of information for the restoration
No mirrors please
Cadence SPB OrCAD 16.5.008 (Allegro SPB) Hotfix
Cadence SPB OrCAD 16.5.00(5,6)7(Allegro SPB) Hotfix
Cadence SPB OrCAD 16.5.00(1,2) (Allegro SPB) Hotfix
Cadence SPB/OrCAD 16.5.000 (Allegro SPB)
All parts on filepost.com, fileserve.com, filesonic.com interchanged. It is added by 5% of the overall size of the archive of information for the restoration
No mirrors please