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Cadence XCELIUM 23.09.003

Posted By: scutter
Cadence XCELIUM 23.09.003

Cadence XCELIUM 23.09.003 | 14.6 Gb

Cadence Design Systems, Inc. , the leader in global electronic design innovation, is pleased to announce the availability of XCELIUM 23.09.003 (XCELIUMMAIN) is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.

AVSREQ-100451 PARSE_SV Support for built-in methods in constant expressions
AVSREQ-100795 DMS_ELAB Aout ports from different L2E seem to be shorted when Din ports connect to the same wire
AVSREQ-100910 DMS_LP_AMS Internal Exception during CPF run with PMC IP in spice
AVSREQ-102183 SYSC_GENERAL Cannot connect SystemC double ports on SV real ports: fatal error or tool crash at elaboration
AVSREQ-103562 SPECMAN_PERF Wrong number provided in case of stack overflow error
AVSREQ-107187 SV_INTERFACE Warn when elaborating virtual interface that has several implementations
AVSREQ-107475 PARSE_SV xmvlog *E EXPSMC for array.size() in solve before constructs
AVSREQ-110533 SV_GENERAL with using unique0 getting *E,MISEXX error message
AVSREQ-111017 SV_GENERAL Is enumerated type method .num considered a constant function?
AVSREQ-111756 PARSE_SV Xcelium gives an error when declaring an array as "type [size] array_name"
AVSREQ-114020 SV_GENERAL Use the regular warning message for $fopen fail
AVSREQ-114518 PARSE_SV xmvlog: *E,SVPKSN (lkp.sv,258|93): The single-bound form of a range is only allowed for array (i.e., unpacked) dimensions.
AVSREQ-114520 PARSE_SV xmvlog: *E,BADQAL (traffic_seq.sv,52|14): Lifetime or qualifier(s) 'static' not allowed before function declaration.
AVSREQ-114596 SYSC_SHELL xmshell option to define shell type name
AVSREQ-117985 DMS_VLOG Misleading error NOTCMP in textDesignCompilation.log when text file included has issues
AVSREQ-120842 SV_GENERAL xmvlog: E,MISEXX : when unique0 is used
AVSREQ-121183 DMS_CONNECT_MOD R2E_2 connect module does not accommodate negative value for vx parameter
AVSREQ-129410 ASSERTION_SVA function not getting called again in an assertion
AVSREQ-129957 PARSE_SV xmvlog: *E,COFILX (test.sv,3|31): cannot open include file '$ABC/dir/file.sv'.
AVSREQ-136586 XRUN_GENERAL Reference compilation option variable in the xrun log file when this one is badly defined
AVSREQ-137073 DOCUMENTATION xrun -pkgsearch needs to be documented
AVSREQ-139331 VPI_GENERAL ERROR: VPI NOPTVA vpi_put_value() cannot place a value into the object of type vpiRealNet
AVSREQ-139437 SV_GENERAL Please add support for unique0
AVSREQ-139713 PARSE_SV SVPKSN, The single-bound form of a range is only allowed for array (i.e., unpacked) dimensions.
AVSREQ-141472 PARSE_SV xmvlog: *E,SVPKSN: The single-bound form of a range is only allowed for array (i.e., unpacked) dimensions.
AVSREQ-144378 SV_GENERAL Sparsearray option to work for multi-dimensional unpacked array as well
AVSREQ-145247 COVERAGE_TOGGLE Toggle coverage for packed union type signal is not supported.
AVSREQ-145302 DMS_SIM AMS simulation leading to internal exception ssl_width_expr
AVSREQ-145844 ELAB_SV Unexpected BNDASW in always_comb
AVSREQ-146190 LP_1801 Support for instance name starting with/on bind_checker command
AVSREQ-146491 SV_GENERAL The "unique0 if" statement in always_comb seems not to supported
AVSREQ-148427 SV_GENERAL Support of sparse array (-sparsearray) for the multidimensional unpacked array
AVSREQ-149503 LP_1801 Rooted Supply Port is corrupted when power model is instantiated
AVSREQ-150075 COVERAGE_ALL_COVERAGES Allow CBV generation in Xcelium to enable parallelism in collected flows
AVSREQ-150104 DMS_ELAB discipline resolution does not change in generate block
AVSREQ-151172 XPROPAGATION_GENERAL xprop – propagate 'x' if one of operand is 'x' in fox mode
AVSREQ-151422 SV_GENERAL Need support for "unique0" in combination with "if" and "case".
AVSREQ-152412 SPECTRE_AMSD SFE-435 error with scalar signals defined with range [1:1]
AVSREQ-153124 SYSC_GENERAL xmelab: *E,SCIPDT: Unsupported 'inp' connection: SystemC double port should be connected to a 64-bit Verilog vector port.
AVSREQ-153178 SV_DPI Request for multi-dimensional dynamic array access support in DPI-C
AVSREQ-153806 MSIE_ELAB *E,INCODP A defparam cannot set the value of a target parameter in another partition
AVSREQ-154395 XRUN_GENERAL Out of stack issue during Xcelium elab (from cu_atstar_expression)
AVSREQ-155265 FUNC_SAFETY_CONCURRENT UNSUPPORTED_BLOCK: DELAY Unsupported - Expr: (VST_E_DELAY_CONTROL) Delay Type: (Blocking delay in loop)
AVSREQ-155883 UVM_REG cdns_uvmreg_utils_pkg.sv at central path is not compiling in new releases
AVSREQ-156122 DMS_WREAL Average-value of wreal.
AVSREQ-157115 COVERAGE_TOGGLE Toggle coverage for unions
AVSREQ-157602 IP_PROTECT_GENERAL Question regarding vulnerabilities with using IEEE 1735 Encryption
AVSREQ-159348 GLS_GENERAL deposit on flip flop is not overriden by when simulator should remove it.
AVSREQ-160200 DEBUG_DESIGN_DATABASE Unable to send enum signals to FSM window
AVSREQ-160683 DMS_ELAB CUVINP for tranif1 primitive and wreal4state
AVSREQ-160804 LP_1801 literals connected to PA models are NOT corrupted when driving PD is OFF
AVSREQ-161501 SIMVISION_MS Add a way to display only analog or only digital signal object in design browser
AVSREQ-161754 ASSERTION_SVA E,SVFORG $past doesn't using default clocking
AVSREQ-161979 SPECMAN_ERRORS Source ref. missing in error message in compiled code
AVSREQ-162899 XPROPAGATION_GENERAL XPDIS when multiply driver not the same array cell
AVSREQ-163144 LP_1801 LP two isolation strategy
AVSREQ-163469 SV_PERFORMANCE slow simulation - callback removal
AVSREQ-163928 LP_1801 OOMR with 1801 UPF issues CUOOMR elaboration error
AVSREQ-165010 SV_PERFORMANCE simulation run very slow ~100s for 1us of simulation
AVSREQ-165387 SV_GENERAL xmvlog: *E,WOUPXR: An expression with an unpacked array datatype is not allowed in this context: unpacked array in forever sensitivity list
AVSREQ-165785 DEBUG_DESIGN_DATABASE SimVision - Reinvoking the Simulation exits xmsim unexpectedly
AVSREQ-165800 SPECMAN_GENERATION Specman crash on gen lint due to constraint contradiction
AVSREQ-165828 SIM_RACEDT How to check race condition in design that include #delay.
AVSREQ-166126 COVERAGE_ALL_COVERAGES Provide read/write api for cbv
AVSREQ-166906 ELAB_SV_VHDL Does MXINDR message point to an illegal construct?
AVSREQ-167506 UVM_REG cdns_uvmreg_utils_pkg.sv in version 21.09 causes compilation errors
AVSREQ-168861 DMS_ELAB internal exception building platform with AMS
AVSREQ-169158 SIM_RACEDT Provide support of register with constant indices Aggregate data type in race detection
AVSREQ-169159 SIM_RACEDT Provide support of force/deposit in race detection
AVSREQ-169317 XRUN_GENERAL need of LD_LIBRARY_PATH setting for specman c function library loading
AVSREQ-169414 MSIE_PERFORMANCE Provide a warning when top level module is defined as primtop without any lower/adjacent incrtop/top
AVSREQ-169441 ESW_IDADBGEN volatile variables shows as Uninitialized in ESW Session
AVSREQ-169994 DOCUMENTATION Document all -msieunlock options in the user guide
AVSREQ-170475 DMS_AXUM AMSD : Spice OOMR is not returning the value for few nets
AVSREQ-170803 LP_1801 OOMR on vhdl port is unsupported with LP 1801
AVSREQ-171290 DEBUG_PROBE SimVision displays wrong values for structs of unpacked arrays
AVSREQ-171525 PARSE_SV Add feature to provide report of uvm_hdl_force & uvm_hdl_deposit calls during parsing
AVSREQ-171650 IP_PROTECT_GENERAL Unable to add breakpoint to TB SV code via indago/simvision GUI
AVSREQ-171816 GLS_SDF Simulation crash (sv_seghandler - trapno -1) Logic primitive 'interconnect delay', single-source, single-long delays
AVSREQ-171925 LP_1801 CUOOMR : with LPS simulation only.
AVSREQ-172068 SIM_SV Software crash with enable_parallel_aa
AVSREQ-172178 PARSE_SV Unable to downgrade NOTDOT with -vlogcontrolrelax NOTDOT.
AVSREQ-172386 ELAB_SV Enhancement Request:ICDPAV relaxation or waiver at a procedure level
AVSREQ-172499 SIM_PERFORMANCE Need continuous assignment optimization for Chisel generated code. Xcelium ~42-45 mins slower than competition.
AVSREQ-172640 GLS_SDF Elaboration crash when using XCELIUM22.03.a001_nosanity.debug.
AVSREQ-172648 LP_1801 CUOOMR when dealing w/ LP
AVSREQ-172699 PARSE_SV xmvlog: *E,BADQAL: Lifetime or qualifier(s) 'static' not allowed before function declaration
AVSREQ-172748 COVERAGE_CODE xmsim INTERR after UVM finish and during xcelium exit
AVSREQ-172979 SV_PARAMETERS SVARPX: Unsupported element datatype for array parameter : -enable_multidim_strparam_uparr
AVSREQ-173130 RAND_DEBUG Enhance RNDOCTO message with 'warn_on_iters' information
AVSREQ-173151 GLS_TIMING Xcelium(21.09 and 22.03) elaboration performance degrade
AVSREQ-173644 VHDL_GENERAL VHDL:STD_DEVELOPERSKIT package in Xcelium install
AVSREQ-173787 ELAB_SV bind failure related to type parameter
AVSREQ-173802 SPECTRE_AMSD AMS Flex with Classic Spectre and certain save options results in incorrect real waveform in ViVA XL
AVSREQ-173838 DMS_PERF Using -dms_perf unable to get through elaboration with *F,AMSIPC error
AVSREQ-174104 PARSE_SV -allowredefinition solution when views are not utilized by user
AVSREQ-174264 DMS_WREAL "assign net = 0" does not work for Verilog-AMS wreal when -dms_real_net_init is used
AVSREQ-174304 LP_COV_VERIFY IMC tool Issue: where PST is visible but PSW info were missing
AVSREQ-174396 SV_GENERAL BIMNCN: Requesting Support for Built-In methods in constant expressions
AVSREQ-174497 MSIE_ELAB Enable -libverbose for MSIE genhref log under -enable_libverbose_genhref
AVSREQ-174578 PARSE_SV CU scope declaration CUDCLR verbosity log with -parseinfo cuscope_verbose need to be made better
AVSREQ-174669 SV_DYNAMIC_DATATYPES EQPCXT: The empty queue primary is only legal in context of a queue or dynamic array
AVSREQ-174865 ASSERTION_SVA xmelab:SVFORG $past not using default clocking in generate block
AVSREQ-175003 XPROPAGATION_GENERAL Incorrect X propagation on arrays.
AVSREQ-175160 LP_1801 need to ignore load_upf when scope does not exist
AVSREQ-175609 DMS_PERF Performance improvement of the UDN profiler Phase 1
AVSREQ-176181 XRUN_GENERAL xmelab INTERNAL EXCEPTION in xrun -hw -compile split flow due to stack memory overflow
AVSREQ-176377 LP_COV_VERIFY Change how lps_cov enables functional coverage
AVSREQ-176707 LP_MSIE xmelab internal error: Finalize iso for primary snapshot needs to be hooked up.
AVSREQ-176775 LP_LIBERTY Spurious LBRTDM message
AVSREQ-176834 PARSE_SV BADRFB, invalid ref argument usage
AVSREQ-177009 DMS_ELAB Invalid SystemVerilog type on mixed-signal connection
AVSREQ-177035 SV_DYNAMIC_DATATYPES xmelab: *E,EQPCXT : The empty queue primary is only legal in the context of a queue or dynamic array.
AVSREQ-177157 DMS_INTERACTIVE Request for probe option that can exclude one or more nettypes
AVSREQ-177294 SV_DPI Need support for Dynamic Array
AVSREQ-177430 LP_1801 Precedence for set_port_attributes / set_related_supply_net
AVSREQ-177506 LP_INFO_MODEL_AND_QUERY Fix bind_checker under-the-hood for parent corner case
AVSREQ-177532 SIM_SV xmsim doesn't return to original directory if a SIGABRT is raised in a different path
AVSREQ-177543 SV_GENERAL E,BIMNCN : Invocation of built-in method in constant expression is not yet supported.
AVSREQ-177620 SYSC_RESET Internal Exception in sc_core::xmsc_in_simulator() when calling reset on an accelerated SystemC testbench
AVSREQ-178058 SYSC_RESET User code in test crashes after "Reset" when SysC is involved
AVSREQ-178259 LP_1801 force does not reapply in upf sim
AVSREQ-178367 DMS_WREAL Request to allow wreal X/Z state in parameters by default
AVSREQ-178646 ELAB_SV xmelab: *E, ASSSTR Continuous assignment. Cannot be applied on Strings.
AVSREQ-178851 SIM_USABILITY CUNOBJ warning about incorrect path
AVSREQ-178950 XRUN_GENERAL xrun: *E,MKDIRP: Unable to create the subdirectory (xllibs)
AVSREQ-178999 DEBUG_PROBE Waves does not have the last clk cycle when a test fails
AVSREQ-179002 SIM_PERFORMANCE Optimization -enable_share_aca causing signals to be X throughout the simulation
AVSREQ-179029 XPESSIMISM_GENERAL Ability to search, modify, and delete paths inside the "encrypted" correction file
AVSREQ-179166 DMS_ELAB To support nettypes through switch primitives – tran, tranif0, tranif1 (*E,CUVINP errors)
AVSREQ-179303 SV_RUNTIME Change error level for "$readmem error: number too long"
AVSREQ-179336 PROFILER_XPROF Adding -xprof in elaboration causing simulation failure
AVSREQ-179417 ASSERTION_COMPILE xmelab interr cuabv_rp_id
AVSREQ-179564 LP_VPI Solution for TCL statement in UPF file - textref recording performance is slow
AVSREQ-179583 SPECTRE_AMSD amsspice: hdl module bus port cannot be in expanded form when it is instantiated in a subckt (spice-in-middle)
AVSREQ-179625 XRUN_GENERAL Apply -roelab only to the compilation phase when using -elaborate and avoid RO_RW_ELAB_WRK
AVSREQ-179671 LP_1801 CUOOMR during LP build only. Without LP it works.
AVSREQ-179787 SV_INTERFACE Constraint solver internal error from constraint accessing port of virtual interface with no read access
AVSREQ-179839 JUPITER_ENGINE MC simulation performance optimization
AVSREQ-180175 DCP rerun simulation trying to write files in original path
AVSREQ-180261 PARSE_SV xmvlog: *F,INTERR: INTERNAL EXCEPTION with Xcelium 22.09.001 with MESSAGE: Unexpected signal #11, program terminated (null)
AVSREQ-180284 XPROPAGATION_GENERAL X-Prop behaviour on array read
AVSREQ-180579 SPECTRE_AMSD Change the *E,RNFNSH message in cgav cases to avoid misunderstanding.
AVSREQ-180580 SPECMAN_TEMPORAL Garbage collection - structs with event @event_ports not removed by quit()
AVSREQ-180668 DMS_WREAL DMS beta option '-dms_real_net_init' causes internal error during AMS sims
AVSREQ-180670 SV_PERFORMANCE Simulation crash with message "INTERR, illegal list underflow"
AVSREQ-180874 SIM_PERFORMANCE -genvtwfile is generating an incomplete vtw file
AVSREQ-180931 XRUN_UVM sim failed with error : function uvm_hdl_deposit not found
AVSREQ-181013 SV_INTERFACE Make VIFUCON a simulation error instead of elaboration error
AVSREQ-181041 FUNC_SAFETY IDDQ performance fix
AVSREQ-181075 LP_INFO_MODEL_AND_QUERY query_pg_info_cell support for extracting power model supply
AVSREQ-181076 LP_INFO_MODEL_AND_QUERY upf_query_pg_info support for extracting power model supply
AVSREQ-181161 GLS_GENERAL GLS - To print the net names whenever glitches occurs in the log file based on the user choice
AVSREQ-181321 MSIE_ELAB HREFAC messages in single-step MSIE and re-elaboration of primaries
AVSREQ-181401 LP_ISOLATION "-source -sink -no_isolation" does not work for split wire
AVSREQ-181408 POWERPLAYBACK_GENERAL Power Playback need an option to stop simulation time at replay end time
AVSREQ-181560 XRUN_GENERAL Facing E,CUVMUR while replacing enable_work_yvlib with enable_single_yvlib
AVSREQ-181617 LP_1801 [LPS] wildcard in UPF can't work for generate block
AVSREQ-181855 DMS_ELAB Show filename and line number for -dms_trace_coercion results
AVSREQ-181858 UVM_SV Input driving an inout
AVSREQ-181860 SIMVISION_GENERAL Color mismatch between trace and trace legend in simvision
AVSREQ-181869 POWERPLAYBACK_GENERAL PowerPlayback : extensions of liberty file list.
AVSREQ-181948 COVERAGE_MERGING toggle coverage not displayed when using set_type_only_coverage after merge
AVSREQ-182007 XRUN_GENERAL Env variables are not evaluated in the xrun.log file when there is a Tabulation in xrunArgs file
AVSREQ-182029 LP_1801 Run time crash while using xrun to run low power simulation
AVSREQ-182124 POWERPLAYBACK_GENERAL [PPB Enhancement ] Processing essential signals from macro (Liberty has) output
AVSREQ-182331 SPECMAN_E UVM-ML enhancement - using uvm_config_set in parallel hierarchy
AVSREQ-182433 VPI_GENERAL Need a single click on class handle to jump to Class definition on source browser
AVSREQ-182513 LP_1801 UPF Parsing perf issue with SPA -is_analog
AVSREQ-182587 COVERAGE_CODE Expression coverage cannot support logic operation with bit width casting
AVSREQ-182687 ELAB_CLONE cu_get_vlogot, cu_dfs_visit_vertex crash with xmclone
AVSREQ-182743 SV_INTERFACE xmelab: *E,CUTMNI due to array of modports in interface.
AVSREQ-182842 SIMVISION_WAVEFORMS SimVision "segment violation" (SIGSEGV) while exporting Waveform
AVSREQ-182860 DMS_SOLUTIONS Auto create -top option under the hood with -dms_udn_profiler
AVSREQ-182891 PROFILER_XPROF Xcelium simulation fails when adding -xprof option
AVSREQ-182894 GLS_TIMING xmelab: *F,INTERR: INTERNAL EXCEPTION, apx - can't abstract pointer, 0x06dbd8 of 0x15ed9868
AVSREQ-183117 XPROPAGATION_GENERAL x-prop option for clk X handling
AVSREQ-183131 DMS_SIM xrun simulation failure linked with multiple usage of $analog_node_alias command
AVSREQ-183142 XRUN_GENERAL Optimize the Stack Size of Xcelium as it results into stack overflow
AVSREQ-183217 LP_INFO_MODEL_AND_QUERY Wrong upf_generic_source/upf_generic_sink values for back-to-back isolations
AVSREQ-183265 ELAB_PERF Internal error with option -enable_forgen_glom_opt
AVSREQ-183304 SV_PARAMETERS NOTDOT error when using a dotted expression that resolves into a member select
AVSREQ-183427 SIM_VHPI Xcelium VHPI callback state undefined
AVSREQ-183456 LP_SV Xcelium simulate unexpected result
AVSREQ-183472 LP_LIBERTY Xcelium report xmelab Internal Exception
AVSREQ-183479 VHDL_GENERAL Incorrect/unexpected simulator behavior in the delta cycles for the vhdl design.
AVSREQ-183535 JUPITER_GL_SC track checkins for AVSREQ-175812
AVSREQ-183576 DMS_LP_AMS Elaboration crash with -dms_perf + UPF in 22.12-A (elaborates fine with -dms_perf and without UPF)
AVSREQ-183608 LP_1801 create a soft error when supply_net_type is not connected to the same type in HDL
AVSREQ-183791 PARSE_SV enhance the warning message to inform the user that line support is extended with ext_src_info
AVSREQ-183935 SIM_SV xmvlog: *E,SCNOIN : As a temporary implementation restriction, the source data type in a static cast must be an integral, real or class data type.
AVSREQ-183945 MSIE_ELAB Indago won't load LWD when one of parallel elaboration was used only on an unused primary
AVSREQ-183961 SIM_PERFORMANCE Enhancement for SSS_KM_FINDRFT performance analysis
AVSREQ-183968 DMS_VLOG Add DMS library by default to the pkgsearch
AVSREQ-183984 XPROPAGATION_PERFORMANCE Xcelium Simulation Too Long (~9x) When Using Switch "-xprop C"
AVSREQ-184222 ASSERTION_SVA xmvlog: *E,SVAFTN (test.sv,2|32): Formal argument does not have an allowed datatype
AVSREQ-184240 SV_PORTS PCRFUP error with ref real interface ports
AVSREQ-184254 FUNC_SAFETY_ELAB array declaration of enum datatype is unsupported
AVSREQ-184258 SIM_SV Mismatch between x86 and aarch64 - negative zero shortreal
AVSREQ-184270 SV_GENERAL unique0 case() not supported
AVSREQ-184289 XRUN_GENERAL xrun: *E,OPTNOML: Multiple -sparsearray option specified, only 1 required.
AVSREQ-184337 SIM_SV Indago interactive is not responding when trying to stop to find the infinite loop
AVSREQ-184383 XPROPAGATION_PERFORMANCE Xprop build time and memory increases when compiling synthesizable RAMS
AVSREQ-184409 SV_PERFORMANCE Newperf option -enable_parallel_aa causes uvm_phase to become null
AVSREQ-184459 SIM_PERFORMANCE Xcelium 18.08-a001 vs. Xcelium 22.12-a071 Performance (simulation time)
AVSREQ-184530 SV_GENERAL Error message in different timescale in the same file
AVSREQ-184626 LP_LIBERTY ILLPRT as .lib.cellindex.cdb.t is not created
AVSREQ-184686 DMS_ELAB AMS elaboration stops with F,INTERR
AVSREQ-184689 PROFILER_XPROF xrun catch internal exception error when advance profiling is enabled using -xprof
AVSREQ-184721 LP_SIM_PERF FF output "q" changes the same time as input "d" changes
AVSREQ-184735 SIM_SAIF_TCF Pending issues from AVSREQ-179451 (Reduce SAIF file information)
AVSREQ-184786 MSIE_ELAB Provide a soft error on starting of MSIE Simulation when any of the elaborated primary snapshots is run with wildcard href
AVSREQ-184790 IXCOM xmelab crash with -genhwaccessfile and -ixcom_dut_info
AVSREQ-184831 SIM_PERFORMANCE different behavior on simulation with vs without dump
AVSREQ-184863 XPROPAGATION_GENERAL disable xprop from being applied to time variable
AVSREQ-184907 LP_1801 Elaboration failed with internal exception with UPF
AVSREQ-184926 LP_1801 unclear elab error INVPFL message
AVSREQ-184976 SIM_PERFORMANCE Compile time X 3-4 than competition
AVSREQ-184978 SPECTRE_AMSD Flex 2.0 and PBSR: re-booting the analog solver after a warm restart causes the simulation to freeze
AVSREQ-184995 SIM_PERFORMANCE Elab crash during MSIE DSS build
AVSREQ-185055 VST_PRIME Higher contribution of ACTIVE POSEDGE WAKEUP(GP)(N)
AVSREQ-185078 SIM_PERFORMANCE Different behavior of Flipflop with and without coverage
AVSREQ-185172 MSIE_SIMULATION simulation error reporting UVM_FATAL
AVSREQ-185188 DMS_LP_AMS AOILPE message does not point to any file or module
AVSREQ-185191 ASSERTION_PERFORMANCE Assertion Performance Improvement
AVSREQ-185329 COVERAGE_COVERGROUP *F,AFAERR Access walk error when using $rtoi with get_coverage()
AVSREQ-185350 COVERAGE_ALL_COVERAGES vManager crashed when taking a snapshot - crash comes from union models
AVSREQ-185360 PARSE_SV expanded macro of OOMR missing textrefs
AVSREQ-185370 PARSE_SV Enable "-enable_macro_include_refs" by default
AVSREQ-185373 LP_INFO_MODEL_AND_QUERY upf_generic_source and upf_generic_sink to support isolation devices when querying for source and sink
AVSREQ-185393 MSIE_ELAB Dump type based href file also with genhref and autohref flow
AVSREQ-185448 LP_1801 Xcelium simulation extra toggle counter
AVSREQ-185458 LP_ISOLATION Elaboration with LP shows large degradation in elaboration time
AVSREQ-185521 LP_1801 Customer : $link_driver_simstate returning "x" for isolation port
AVSREQ-185623 ELAB_BIND Internal error in simulation from customer's AI team
AVSREQ-185629 ESW_SYMBOLICDEBUG ESWD: Indago crash when moving debug time cursor on waveforms
AVSREQ-185640 RAND_SOLVER Unexpected randomization result
AVSREQ-185688 SV_BUILD_PERF Add -enable_constfn_opt under newperf umbrella
AVSREQ-185706 MCP_SIM MCP_SIM: Build profiling infrastructure for perf debug of MCP simulations
AVSREQ-185708 ELAB_SV Provide Warning YYYY package lib1.pkg (file,line of package declaration), package lib2.pkg (file,line of package declaration), .. package libn.pkg (file,line of package declaration) contains non integral datatype, enum, global static variable
AVSREQ-185710 ELAB_SV Provide Warning ZZZZ packages lib1.pkg (file,line of package declaration), lib2.pkg (file,line of package declaration),. libn.pkg (file,line of package declaration)have the same package name and are different
AVSREQ-185748 SIM_PERFORMANCE Xcelium is 1.13X slower than reference
AVSREQ-185817 VWDB_XCELIUM Native FSDB dumper freezes after xmsim-aid is done
AVSREQ-185888 ELAB_CLONE Simulation failure observed when building with -xmclone
AVSREQ-185908 MSIE_ELAB Getting VIFUCOM in single-step MSIE
AVSREQ-185911 GLS_GENERAL deposit to signals of connect to tranif1 behavior is not as expected
AVSREQ-185918 PROFILER_SIM_RUNTIME Add number of clocks to design summary section at the end of elaboration
AVSREQ-185964 POWERPLAYBACK_GENERAL Power Playback mapping rate is not correct
AVSREQ-185965 SIM_SV_VHDL $export_frcrel does not work for VHDL on Xcelium 22.04.a071 and later version
AVSREQ-185970 PARSE_SV Macro nesting gets a NOTDIR error
AVSREQ-186007 DMS_SIM Using $dumpvars on UDN leads to an Internal Exception
AVSREQ-186009 LP_1801 GLS UPF flatten hierarchy ILLPRT errors for escaped names
AVSREQ-186027 LP_SIM_PERF xmsim 4.7X RTL/UPf
AVSREQ-186040 SIM_PERFORMANCE Make genvtwfile the default option
AVSREQ-186099 SIM_SV unexpected x in simulation
AVSREQ-186125 FUNC_SAFETY_CONCURRENT Xcelium23.01.i339 crashes during fault concurrent run
AVSREQ-186126 ELAB_SV assign statement not giving desired results with if(1) code statement
AVSREQ-186163 ELAB_SV Provide Warning XXXX packages lib1.pkg (file,line of package declaration), lib2.pkg (file,line of package declaration), libn.pkg (file,line of package declaration) have the same package name and are identical
AVSREQ-186170 SIM_PERFORMANCE Removing -linedebug from compilation leads to crash
AVSREQ-186256 SIM_SV svh_getpibforvstfromrtti - !rttip super internal exception when probing
AVSREQ-186259 SPECTRE_AMSD AMS interactive: Support Flex 2.0 and Homogenous-PBSR
AVSREQ-186275 PARSE_SV Introducing new warning for pre_randomize task to help - xmsim crash with message: T(0) sv_seghandler m_wait_for_arbitration_completed
AVSREQ-186276 PARSE_SV E,MIMPST - Identifier cannot be resolved; error is not reported if one package is imported in CU scope
AVSREQ-186277 PARSE_SV solver crashed with message: svrnc_trat_update_value_variable_auto
AVSREQ-186284 ELAB_SV Provide lib.cell:view information in TYCMPAT error for interface/virtual interface compiled in two libraries
AVSREQ-186328 LP_1801 link_driver_sim_state driver from liberty
AVSREQ-186346 LP_INFO_MODEL_AND_QUERY Wrong retention clk/rst driver tracing
AVSREQ-186441 ASSERTION_COMPILE INTERR with message tl_abv_pw_optim_block_qualifies - sampling always block has less than 2 statements
AVSREQ-186453 VST_PRIME xmelab crash with latest nightly agile (build w/ synth. rams) #1
AVSREQ-186466 COVERAGE_FUNCTIONAL Demote CUCRBM to warning, bin-merge mode should be ignored by any covergroup/cross that doesn't support it
AVSREQ-186468 SPECMAN_INDAGO xmsim crashes after issuing simulator reset - Specman interactive
AVSREQ-186501 RAND_SOLVER Low randomization seed dispersion from xrun to vmanager
AVSREQ-186508 SIM_SV Xcelium string match function doesn't work as expected
AVSREQ-186513 SIM_PERFORMANCE Internal error (gwm_filter CUV_NL default) when elaborating GLS env.
AVSREQ-186545 LP_1801 21.03.013 works, 22.09.003 tool crash
AVSREQ-186546 LP_1801 find_objects matches to many pattern compared to CLP and third-party tool
AVSREQ-186558 DEBUG_DESIGN_DATABASE Verisium Debug does not respond to driver tracing of a clock signal
AVSREQ-186559 DEBUG_DESIGN_DATABASE Verisium Debug does not respond to driver tracing of a clock signal
AVSREQ-186561 LP_ISOLATION Why does -exclude_elements not apply when location is fanout?
AVSREQ-186667 DEBUG_COMMAND Indago executable erroring out with VERISIUM_DEBUG_ROOT
AVSREQ-186694 LP_1801 isolation detailed query needs an additional field for b2b iso
AVSREQ-186700 POWERPLAYBACK_GENERAL Powerplayback needs to support gz file for mapping file
AVSREQ-186702 POWERPLAYBACK_GENERAL Powerplayback needs to support presim offset by percentage
AVSREQ-186787 PROFILER_SIM_MEMORY memory profiler reports high memory usage vs heap
AVSREQ-186793 SPECTRE_AMSD SystemC elab crash with an EHF
AVSREQ-186862 FUNC_SAFETY_ELAB *F,INTERNAL EXCEPTION seen when fault switches are added.
AVSREQ-186889 SPECTRE_AMSD Usage of $sformatf inside a generate statement with for loop causes segmentation fault
AVSREQ-186914 SIM_SV illegal list underflow fatal error
AVSREQ-186915 DMS_SOLUTIONS Timescale changes
AVSREQ-186922 FUNC_SAFETY_XFR xfr hangs when fault_strobe is used
AVSREQ-186926 XRUN_GENERAL "-cassign_self_trigger" would not get applied using XMELABOPTS
AVSREQ-186928 SIM_SAIF_TCF Xcelium dump SAIF sum of T0 / T1 is not equal to duration
AVSREQ-186930 PROFILER_SIM_MEMORY Xcelium memory profiler has an instance item that exceeds 100% issue
AVSREQ-186931 PROFILER_XPROF Enhanced requirements for the profiler require a CPU usage summary section - TB/DUT/UVM/C Call Allocation/DPI/Others(only related to simulator)
AVSREQ-186939 POWERPLAYBACK_GENERAL Create mapping file by identifying macro cell instantiations
AVSREQ-186955 LP_LIBERTY xmelab crash due to cdb file
AVSREQ-186976 LP_RETENTION Retention should not be allowed on GL sequential elements
AVSREQ-186986 JUPITER_COMPILER MC_DFT_CUST: Elaboration crash in Splitting "huge fanin found, new split max size is too big" in multiple DFT tests
AVSREQ-186989 PARSE_SV Customer codes report *E,NOTDIR but can pass with competition
AVSREQ-186992 DMS_MSIE INTERNAL EXCEPTION: sv_seghandler - trapno -1 addr(nil)
AVSREQ-187033 SV_PARAMETERS xmelab crash issue : dto_range_width - no width
AVSREQ-187044 IP_PROTECT_GENERAL Break point is not set inside main phase of class test in indago
AVSREQ-187054 SIM_PERFORMANCE elab crash on multi xrun MSIE flow
AVSREQ-187055 PARSE_SV wrong parameter computation in 22.12-a001 and up
AVSREQ-187087 SIM_PERFORMANCE Post sim for SoC- pass with SDF min but Fatal with SDF max
AVSREQ-187094 MCP_SIM MCP violation is not detected if testbench has additional timescale settings
AVSREQ-187104 MCP_ELAB MCPSKP & 'No MCP source found in destination' are reported
AVSREQ-187131 LP_RETENTION nc_global_floating_supply_net when using LPS_RTN_HYBRID
AVSREQ-187145 UVM_ML_OA_FRAMEWORK wrong translation in vhpi2val in umm
AVSREQ-187154 XRUN_GENERAL SCCLNG description not in sync with the tool installation versions
AVSREQ-187155 DMS_AXUM During Mixed signal simulation, xrun fails with the ?xmelab: *F,INTERR: INTERNAL EXCEPTION? error
AVSREQ-187158 DEBUG_DEP Missing isolation hybrid elements
AVSREQ-187162 SIM_SAIF_TCF Xcelium misses dumping some instances in SAIF
AVSREQ-187261 SR_XEML Xcelium ML Plug n Play support for 3 step Xcelium flow
AVSREQ-187276 SIM_PERFORMANCE MEMPC warning due to *enable_memopt*
AVSREQ-187362 PROFILER_MEM_XPROF memory profiler (-mem_xprof) crashes after profile -clear command
AVSREQ-187369 SIM_PERFORMANCE -enable_memopt_partial_vst leads to reelab in MSIE dss rebuild
AVSREQ-187370 SPECTRE_AMSD AMS causes *E,SYERROR and *F,SSIGF: Analog elaboration failed
AVSREQ-187386 CORE_RAND Update distreport.py for all random variable analysis
AVSREQ-187388 CORE_RAND Fix inconsistency between hex and decimal representations in dist reports
AVSREQ-187391 CORE_RAND Updates to dist analyzer command-line and defaults
AVSREQ-187419 LP_1801 Simulation wrong behavior related to combination of LP, bind statement, interface and force
AVSREQ-187436 LP_1801 'x' on a HDL net which has 2 loads:HDL and UPF(+lib)
AVSREQ-187450 SIM_SV Are there any XLM optimizations around uvm_object::get_inst_id?
AVSREQ-187460 DEBUG_DESIGN_DATABASE Explore connectivity shows wrong generate block connection
AVSREQ-187469 LP_INFO_MODEL_AND_QUERY Simulation crash
AVSREQ-187470 VHDL_CODEGEN xrun: *E,VHLERR: Error during parsing VHDL file
AVSREQ-187477 VST_PRIME CPU: T264 cluster 1.7x slowdown wrt reference
AVSREQ-187489 XPESSIMISM_GENERAL Provide modify/replace and delete path facility from a text file
AVSREQ-187493 DCP dcp -replay shows error, xrun: *E,SPCERR: The program encountered one or more errors while processing the input SPICE file(s) in the AMSD flow.
AVSREQ-187536 SIM_PERFORMANCE register is not updated on rising edge when all conditions are met
AVSREQ-187548 SV_PARAMETERS Parameter Computation Crash with "-enable_enh_param_arch"/"newsv" in 22.12-a and up
AVSREQ-187561 ELAB_VHDL Auto MSIE flow exhibits unexpected behavior - VHDL COD getting updated unexpectedly
AVSREQ-187564 SPECTRE_AMSD AMSD:Spectre X: Monte-Carlo - simulation exiting because of $finish from E2L_2_dynsup.vams CM
AVSREQ-187617 COVERAGE_PERFORMANCE Degraded build performance with coverage enabled
AVSREQ-187642 LP_INFO_MODEL_AND_QUERY Phase-1: Enhance and test SV Information Model to support mixed language paths
AVSREQ-187661 DEBUG_DESIGN_DATABASE Cannot trace release statement
AVSREQ-187684 XRUN_GENERAL Build crash Internal Exception
AVSREQ-187689 ELAB_BIND crash during simulation with MESSAGE: T(0): sv_seghandler - trapno -1 addr(0x18)
AVSREQ-187700 SIM_SAIF_TCF Xcelium dump SAIF IG field with -ewg option
AVSREQ-187701 SIM_SV Need better debug messages when xmsim exits w/ 255 exit code due to user C/C++ code
AVSREQ-187718 ELAB_SV Supporting access to struct member/ class register of basic types within interface through a virtual interface
AVSREQ-187766 SR_BACKDOOR SVRNC can't get class name of struct when CU scope typedef is used
AVSREQ-187768 SIM_PERFORMANCE Simulation performance tracking for ad10y design in secure chamber
AVSREQ-187779 SIM_PERFORMANCE xmvlog_cg crash
AVSREQ-187782 DEBUG_DESIGN_DATABASE Cannot trace driver from a bit signal of a bus in generate block
AVSREQ-187808 SIM_SAIF_TCF Xcelium miss dump SRAM instances which describe in input forward SAIF in new format SAIF
AVSREQ-187814 SIMVISION_MS SimVision MS: allow sending multiple selected signals to ViVA
AVSREQ-187815 LP_1801 [EP Connectivity UPF PARTL] Failure of simple signal assignment resulting in XOSC clock failure
AVSREQ-187827 SIMVISION_MS SimVision Schematic Tracer: do not lose focus from zoomed area when collapsing an instance
AVSREQ-187854 ELAB_PERF XMELAB: Perf improvement request from ~1hr:54min to ~1hr
AVSREQ-187940 ELAB_BIND Make -showtoplcv feature available under -showalllcv / -alllcv_file
AVSREQ-187944 DEBUG_PROBE '-nowarn PRPSWM' does not suppress visadev warnings during xrun elaboration
AVSREQ-187945 LP_1801 Enhance -LPS_REPLAY_UNSYNTH_CA to use release -keepvalue at power-up
AVSREQ-187950 COVERAGE_COVERGROUP [DCSG]Getting TYCMPAT Compile error after enabling Coverage switches
AVSREQ-188056 SIM_LICENSE Support APP_ONLY license check out
AVSREQ-188061 SV_INTERFACE RNDCNSTE and Crash: interface in constraint
AVSREQ-188065 VST_PRIME xmelab crash observed with "-xform_lite Split_Suspendable_Block "
AVSREQ-188066 VST_PRIME xmelab crash observed with "-xform_lite Ff_Split
AVSREQ-188088 FUNC_SAFETY_ELAB Hang seen during incremental elaboration
AVSREQ-188094 SV_PORTS xmelab: *E,CICAPC
AVSREQ-188103 LP_1801 irrelevant UNDVCT when liberty model is loaded
AVSREQ-188111 DEBUG_DESIGN_DATABASE Driver tracing stops responding when tracing a certain signal
AVSREQ-188113 SIM_SV Indago not pointing to hang in case of function calling itself
AVSREQ-188124 LP_1801 Enhance -lps_lib_pg_logic to support supply_net_type
AVSREQ-188129 FUNC_SAFETY instances missing in DHE
AVSREQ-188199 DMS_LP_AMS UPF power supplies are not propagated in electrical context
AVSREQ-188244 DEBUG_DESIGN_DATABASE Improve driver grading performance for always blocks like @(*)
AVSREQ-188256 MSIE_SIMULATION 2x sim slowdown using msie_dss and msie_parallel
AVSREQ-188257 PARSE_SV Unexpected *E,UNDIDN
AVSREQ-188271 XRUN_GENERAL -snapshot overridden by +name+ without error
AVSREQ-188277 LP_1801 No IEEE 1801/design object when using UPF set_design_attributes
AVSREQ-188292 SIM_PERFORMANCE Customer's full chip internal error on incremental snapshot build in VTW sanity checker with '-disable_share_ca_build'
AVSREQ-188328 LP_LIBERTY ILLPRT error as .lib.cellindex.cdb.t is not created when CDS_IMPLICIT_TMPDIR is used
AVSREQ-188336 DEBUG_DESIGN_DATABASE Missing textref when using LWD
AVSREQ-188340 DMS_AMSD $SIE_input function gives different results in 20.05.v001 and 22.04.v003
AVSREQ-188373 DEBUG_DESIGN_DATABASE Wrong active driver - force statement's control logic not considered
AVSREQ-188587 SIM_SV *F,INTERR using VIP (PCIE, NVM) during Migration
AVSREQ-188605 LP_1801 LP behavior is changed with lps_new_ln_support
AVSREQ-188619 SIM_SV 22.12.a071 xmsim sv_seghandler - trapno -1 Anonymous continuous assignment
AVSREQ-188636 SPECTRE_AMSD xmsim: *F,INTERR: INTERNAL EXCEPTION with probe statement
AVSREQ-188766 RAND_DEBUG Tool shows different SEED value between the value passed in the command and in the log (SVSEED)
AVSREQ-188768 SIMVISION_DESIGN_BROWSER Auto Inserted Connect Module option in Simvision is not working as intended.
AVSREQ-188784 ASSERTION_COMPILE Simulation Crash on 23.03-a071-20230308
AVSREQ-188791 SIM_PERFORMANCE Logic signal is not assigned in a nonblocking assignment
AVSREQ-188796 SIM_SV Driver tracing returns no results for a signal that is defined by a struct type parameter
AVSREQ-188799 SIM_PERFORMANCE -enable_var_opt_core option part of newperf causing xmelab: *E,SOLVNT Streaming concatenation expression of nets is not a legal lvalue.
AVSREQ-188804 DMS_ELAB sv_seghandler - trap no -1 when using -dms_mda_2_e option along with -disres=detailed
AVSREQ-188836 DMS_LP_AMS MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-188842 GLS_PERFORMANCE and gate has wrong unknown output
AVSREQ-188850 SIM_SV xmsim crashed when running with fsdb dump.
AVSREQ-188872 SPECTRE_AMSD Xcelium not able to dump proper mixed-signal waveform database
AVSREQ-188952 COVERAGE_TOGGLE Unclear *W,COVNOEN warning in the toggle coverage
AVSREQ-188970 SIM_SV xmsim INTERR in DMS sim but stack doesn't show culprit
AVSREQ-188974 MSIE_PERFORMANCE Put -msie_genhref_skip_clones under -msieunlock simperf
AVSREQ-188980 GLS_GENERAL The wires used within tranif0 and tranif1 are throwing "X" which is unexpected.
AVSREQ-189003 ELAB_SV Concept of logical deadcoding is required to be extended for task.
AVSREQ-189012 SIM_SAIF_TCF Xcelium dump forward SAIF instance need to dump from NET to PORT
AVSREQ-189014 POWERPLAYBACK_GENERAL Power Playback need to support parallel run when shared elaborate database
AVSREQ-189015 DMS_LICENSE How to set lic order for DMS + Single core simulation
AVSREQ-189028 SPECTRE_AMSD xmsim: *E,SYFATAL (****): Illegal port instantiation.
AVSREQ-189040 PROFILER_SIM_RUNTIME Enable profiler if only -prof_dump_interval is provided
AVSREQ-189053 SV_RUNTIME $finish location from encrypted sv file
AVSREQ-189057 SIM_SV $readmemh load to multidimensional array is not showing any changes on waves
AVSREQ-189105 MSIE_ELAB MSIE DSS mode run takes huge time on genhref hierarchy instantiation
AVSREQ-189147 DMS_ELAB Fatal error during schematic/mixed simulation
AVSREQ-189194 LP_1801 support for is_pad in green release
AVSREQ-189209 SR_XEML Xcelium crashes with -ml (likely from -nolog)
AVSREQ-189221 ASSERTION_COMPILE Compilation issue results in Internal Exception error
AVSREQ-189222 ASSERTION_SIM Assertion -off and $assertoff cannot penetrate encrypted module in path for immediate asserts
AVSREQ-189224 SV_INTERFACE xmelab crashed with MESSAGE: cuv_ev_mconnections (bt: cs_ev_vlog_module_3)
AVSREQ-189272 LP_ISOLATION Can't be Isolated From Isolation Rule
AVSREQ-189285 MSIE_PERFORMANCE enable -msie_genhref_skip_clones automatically with AutoMSIE and create a disable option
AVSREQ-189304 SPECTRE_AMSD Crash with AMSD (Flex)
AVSREQ-189324 DCP The "-A" option is not available on strace
AVSREQ-189379 RAND_GENERAL xmsim failed when simulation paused at breakpoint and solver timeout exceeded
AVSREQ-189424 SIM_SAIF_TCF Simulation crashes with an internal error when executing the dumptcf command
AVSREQ-189433 DEBUG_COMMAND remove -lps_1801_msg lps_msg.log from indago_pp
AVSREQ-189447 LP_MSIE MESSAGE: pwr_finalize_iso - Finalize iso for primary snapshot needs [xxx] to be hooked up
AVSREQ-189463 PARSE_SV Unexpected BNDWRN in new xcelium version with parameter propagation list optimization enabled
AVSREQ-189466 DEBUG_DESIGN_DATABASE RC kit shows that elab exits unexpectedly with -lwdgen
AVSREQ-189527 PARSE_SV Parameter assignment is not taking effect on interface instantiation
AVSREQ-189529 SV_INTERFACE SystemVerilog construct not yet implemented:extern tasks within an interface.
AVSREQ-189537 COVERAGE_COVERGROUP Elaboration crash due to super_prune
AVSREQ-189566 FUNC_SAFETY_CONCURRENT concurrent engine could not detect CO of STL safety mechanism
AVSREQ-189638 XM_UTILS_GENERAL Support $xm_mirror_force with unpacked arrays
AVSREQ-189652 SIM_SV Simulation internal error in customer design due to task/ function inline
AVSREQ-189686 ELAB_SV Internal error during elaboration during static analysis in customer environment.
AVSREQ-189702 LP_1801 Unexpected compile with -lps_upfpkg_auto_compile_off
AVSREQ-189743 DEBUG_DESIGN_DATABASE Enhancement request to automatically enable -setenv setting for lwd_complete
AVSREQ-189783 SV_GENERAL SVNETA in elaboration while using default_port_array_wire in compilation
AVSREQ-189789 DMS_AMSD SystemVerilog cged() function does not accept indexed array parameter
AVSREQ-189790 ASSERTION_COMPILE SFLNOS streaming concatenation operator in this context is not supported
AVSREQ-189796 DMS_LP_AMS Xcelium crashes at elaboration with AMS LP simulation
AVSREQ-189804 SPECMAN_UVM_E UVM vr_ad e : incorrect return type in vr_ad_msg_config.e file
AVSREQ-189817 RAND_SOLVER RNDOCTO error when using $countbits in a constraint
AVSREQ-189832 LP_1801 link_driver_sim_state driver does not work for liberty instance array
AVSREQ-189843 SIM_PERFORMANCE Fatal error when enabling waveform dump xmDumpvar for gate-level simulation with sdf
AVSREQ-189870 LP_1801 Xcelium report Internal Exception in xmelab stage when running low power simulation with EHF 2304_e177
AVSREQ-189877 RAND_GENERAL Soft constraints issue during migration
AVSREQ-189901 SIM_PERFORMANCE Removing -disable_new_default_perf switch from compilation leads to crash
AVSREQ-189905 CORE_RAND Casting to unsigned does not work in constraints
AVSREQ-189939 RAND_SOLVER Wrong solution on customer Design
AVSREQ-189949 XM_UTILS_GENERAL xmls crash with MESSAGE: Unexpected signal #6, program terminated (null)
AVSREQ-190024 DMS_LP_AMS Incorrect invalid parameter state_threshold=1 warning message generated
AVSREQ-190035 SIM_PERFORMANCE Clock is not toggling with -enable_clkgen_opt and -enable_rtow_write options used
AVSREQ-190044 PARSE_SV Simulation failing due $size in part-selection not working correctly with -enable_ppl_opt
AVSREQ-190114 LP_ISOLATION minimal UPF from xrio crashes xmelab, design runs clean without
AVSREQ-190122 SV_GENERAL xmvlog: *E,MODPXE (modport.sv,6|19): Unsupported modport expression for port identifier 'srdy'.
AVSREQ-190124 LP_1801 upf annotation failed when retention_name is ret
AVSREQ-190198 PARSE_SV type comparison gives compile fail on mismatch
AVSREQ-190199 RAND_SOLVER RNC flags check_solve_results=15
AVSREQ-190201 LP_BUILD_PERF PA simulation stuck at checkpoint Low Power - after pwrImPowerModel
AVSREQ-190212 PARSE_SV extend enable_cu_deppkg_opt to remove packages imported to CUscope from the CU scope depended list
AVSREQ-190238 COVERAGE_COVERGROUP Unexpected unique items in merged db
AVSREQ-190269 ELAB_CLONE Primary is getting updated with HREF when DSS with xmclone is run on customer's FC design
AVSREQ-190270 MSIE_ELAB Single xrun DSS flow genhref does not get msie genhref skip clone optimization applied
AVSREQ-190285 PARSE_SV value not propagating in an instance
AVSREQ-190297 SV_PERFORMANCE xmvlog_cg *F, INTERR in MSIE flow: gq_svpeep_csfmt_ccall_helper - not a TMP
AVSREQ-190370 ASSERTION_SVA Assertion failure starting in 23.03.v001
AVSREQ-190371 XPROPAGATION_GENERAL Xprop read with invalid index (from array w/ ALL initialized indices) returns x's
AVSREQ-190385 SV_GENERAL Tool giving MODPXE error with ENV CADENCE_ENABLE_AVSREQ_44909_PHASE_1/2 enabled
AVSREQ-190423 POWERPLAYBACK_GENERAL Powerplayback: elements of packed vectors not replayed correctly, when element of packed vectors are specified in signal list file.
AVSREQ-190452 DMS_LP_AMS Generate Soft Error when making analog connection to PSN without correct command line options
AVSREQ-190456 DMS_LP_AMS -auto_config_svams_ie should generate IE card without needing to point to Spectre Install
AVSREQ-190489 PARSE_SV Parameter assignment not taking placing in a module instantiation due to -enable_ppl_opt
AVSREQ-190492 SV_DPI Request enhanced messaging for: xmsim: *E,NULLPT: NULL Scope passed to the svSetScope function.
AVSREQ-190528 ELAB_SV Elaboration internal error in customer design
AVSREQ-190539 SV_PERF Weird ref array behavior in [22.09.v003]
AVSREQ-190541 SV_CODEGEN Xcelium getting crash during migration activity
AVSREQ-190547 PARSE_SV Indago keeps on crashing with message Connection to Design Database (Snapashot or LWD) has been lost
AVSREQ-190554 DMS_CLONE XMCLONE causes $CGED to fail (with -xmclone_uncauterize tran)
AVSREQ-190579 SIM_SAIF_TCF SAIF: Support ZEBU format of dumping
AVSREQ-190594 LP_1801 Elaboration with UPF got crashed
AVSREQ-190598 PARSE_SV Support for *E, SVPKSN error
AVSREQ-190647 RELEASE_INSTALLATION Where are OSVVM examples in a XCELIUM installation directory hierarchy?
AVSREQ-190677 PARSE_SV xmvlog: *F,TOOMTS: more than one -VTIMESCALE option
AVSREQ-190682 SV_PERFORMANCE [DCSG] Xcelium Run time performance slow down the simulator seen HMU Block
AVSREQ-190683 ELAB_BIND xmelab MESSAGE: vst_class() - not in range: 32 with latest AGILE debug kit
AVSREQ-190757 UVM_REG <xcelium_inst>/tools.lnx86/sia/lib/sv/cdn_reg/utils/cdns_uvmreg_utils_pkg.sv conains syntax errors
AVSREQ-190762 LP_1801 driver in interface is not being driven out in 22.09.v003, but is driven out in 22.03.v007
AVSREQ-190773 ELAB_CLONE OBINXZ error when xmclone is enabled
AVSREQ-190776 COVERAGE_FUNCTIONAL xmvlog_cg error at the end of elaboration
AVSREQ-190845 ELAB_SV Waits on task's input args are required to be optimized if that input is not getting modified inside the task
AVSREQ-190863 SPECMAN_E reflection create_new, to create instance of exact subtype
AVSREQ-190864 PARSE_PERF cu_xcenode , cu_doppl crash on new Green release
AVSREQ-190885 DEBUG_DESIGN_DATABASE Part-selection controlled by a for-loop is not working in browser annotation for LHS
AVSREQ-190897 RAND_GENERAL RNDXZW issue with unpacked struct
AVSREQ-190905 DMS_PERF Performance improvement of the UDN profiler Phase 2
AVSREQ-190923 LP_1801 internal power is not powering / output has wrong value
AVSREQ-190924 SV_RUNTIME Presence of uvm_info or $display Statement changes simulation outcome
AVSREQ-190943 SV_INTERFACE TYCMPAT error - parameterized virtual interface, actual and formal args matching
AVSREQ-190961 GLS_GENERAL tranif1 behavior is not as expected when ctrl is changing to 1
AVSREQ-190978 MSIE_ELAB DSS: crash at incremental elab with afile and genhref - MM hybrid
AVSREQ-191030 CORE_RAND Generate executable from distreport.py and add to release kit
AVSREQ-191032 CORE_RAND Generate compact text report for all random variables distribution analysis
AVSREQ-191033 CORE_RAND Change distreport.py script interface to simplify user experience
AVSREQ-191041 FUNC_SAFETY_CONCURRENT fault simulation memory usage and performance improvement
AVSREQ-191064 ELAB_SV xmelab: *F,MCCGLG: Unable to open multi-core CG log
AVSREQ-191099 VHDL_PARSE Compilation issues in the VHDL code
AVSREQ-191123 VHDL_PARSE *E ILSRFC during VHDL code compilation
AVSREQ-191178 SIM_PERFORMANCE Elaboration crash due to -enable_abv_gprune and -no_abv_gprune doesn't work.
AVSREQ-191189 LP_VPI "-debug_opts indago_pp" made primary elab for LPS take very long time caused by empty element lists
AVSREQ-191211 MSIE_ELAB Incremental failed with additional href and afile - follow up to this jira, https://jira.cadence.com/browse/AVSREQ-191210
AVSREQ-191231 RAND_SOLVER [DCSG] xmsim: *W,SVRNDF The randomize method call failed.
AVSREQ-191232 ELAB_PERF Add option -enable_skip_if_hash_remove under either newperf, buildperf or make default
AVSREQ-191321 SV_RUNTIME "%0d" can not be recognized correctly by some Xcelium new releases
AVSREQ-191323 LP_1801 LPS Fail with Cannot Updated Signal Value with Signal Type: realtime, bit
AVSREQ-191371 VHDL_PERFORMANCE Internal exception with 22.09-s004 : sslu_getnscalars
AVSREQ-191373 PARSE_SV Command-line options to set the "CADENCE_ENABLE_AVSREQ_44905_PHASE_1" and "CADENCE_ENABLE_AVSREQ_63188_PHASE_1" environment variables in the 3-step process flow
AVSREQ-191379 SPECMAN_INTEF High memory consumption and leak by xmsim
AVSREQ-191404 SV_RUNTIME Xmsim retains the .nfsXX file until the end of simulation, even after deleting it
AVSREQ-191408 SV_PERFORMANCE VHPI errors with newperf
AVSREQ-191429 LP_1801 signal does not wakeup when PD is on
AVSREQ-191433 IXCOM MESSAGE: sv_seghandler - trapno -1 addr((nil)) at xmelab
AVSREQ-191435 XRUN_GENERAL Ignore irrelevant options while parsing the xrun command
AVSREQ-191487 ELAB_SV Elaboration internal error in customer design
AVSREQ-191488 SIM_PERFORMANCE Simulation with Xprop is very slow (latches not getting pruned)
AVSREQ-191513 RAND_PERFORMANCE utrace and xmprof time for randomization calls mismatches
AVSREQ-191518 ELAB_SV xmelab $info messages are not displaying scope information as expected from protected code
AVSREQ-191523 COVERAGE_PERFORMANCE Over 60% of simulation time spent in two covergroups
AVSREQ-191604 SV_GENERAL deposit values from specman at time 0 do not succeed for logic of more that 32 bits
AVSREQ-191623 DCP Xmdcp replay simulation issue in PBSR testcase
AVSREQ-191633 SV_PORTS Elab crash with LPS
AVSREQ-191682 ELAB_SV Request for support on *E, BIMNCN error
AVSREQ-191712 LP_BUILD_PERF [LPS] Xcelium low power simulation elaboration performance behind OT about 1 hour
AVSREQ-191719 VPI_GENERAL Competition connection program VPI issue ; ERROR: VPI NOTOTI The operation vpi_iterate(vpiReg, …) is not supported for a reference handle of type vpiClockingBlock ; ERROR: VPI NOTOTI The operation vpi_iterate(vpiRegArray, …)
AVSREQ-191723 SV_INTERFACE Support for extern tasks within an interface
AVSREQ-191750 SR_XEML Improper parsing of xeml_drm_cmd_args
AVSREQ-191822 LP_1801 xmvlog: *E,NOPBIND Package uvm_pkg could not be bound, seen when -lps option is added
AVSREQ-191827 SV_PORTS We are seeing a fatal error when we try to elaborate netlist with SDF.
AVSREQ-191852 SIM_PERFORMANCE xmelab crashes with cu_qualify_fanout_to_sps : xsps_1==xsps_2
AVSREQ-191858 DEBUG_PROBE Exclude scope in probe does not work with VWDB
AVSREQ-191874 SIM_PERFORMANCE *F INTERR with tool version later than 22.09 related to always block
AVSREQ-191935 ELAB_PERF incorrect parameter values in elaboration (*E,ERRORE)
AVSREQ-191940 MSIE_ELAB -enable_libmap_with_yv with automsie : xrun: *E,STICNF: A combination of -LIBMAP and -COMPCNFG is not allowed with single step xrun.
AVSREQ-191961 PARSE_SV autofetch: The signal loses scope while backtracing and annotations also vanish
AVSREQ-191972 XRUN_GENERAL Fix all places in xcelium and related tools where hostname + pid is assumed unique
AVSREQ-192036 SIM_PERFORMANCE IOA Core Block Code Gen Crash Issue
AVSREQ-192065 DMS_ELAB -dms_limit_trace_coercion using default limit causes "NOUNIT" elab error
AVSREQ-192067 COVERAGE_PERFORMANCE High memory consumption during coverage dumping
AVSREQ-192075 SR_XEML xeml_update_json changes whitespaces
AVSREQ-192081 SR_XEML xeml_update_json uses wrong string for pass/fail
AVSREQ-192172 DEBUG_DESIGN_DATABASE Elab crash with -xmclone
AVSREQ-192178 SIM_PERFORMANCE Continuous assignments consuming most of the simulation time
AVSREQ-192186 SV_GENERAL Xcelium's interpretation of Testbench causing failures
AVSREQ-192188 SAVE_RESTART_DMTCP Issue during restart on SLES12
AVSREQ-192190 VHDL_GENERAL std_regpak library missing from the STD_DEVELOPERSKIT in the Xcelium install
AVSREQ-192222 MSIE_SIMULATION Enable performance optimization by default for customer array fanout scenario
AVSREQ-192227 SIM_SV Simulation crash with sv_seghandler - systf_sformatf_cpfms.cold
AVSREQ-192270 ELAB_SV got *E,CUVTNH when using SV bind
AVSREQ-192271 SIM_SV Tcl command "value -keys" does not interpret an associative array in SystemVerilog correctly
AVSREQ-192273 ELAB_PERF Optimize label_ot_t generation in OT for internal assertion implementation
AVSREQ-192282 SV_GENERAL What is order of execution of pop_front in {q.pop_front(),q.pop_front()}?
AVSREQ-192285 PARSE_SV INTERNAL EXCEPTION with MESSAGE: apx - can't abstract pointer, 0x29ea740 of 0x7ffff6ae6588
AVSREQ-192289 PARSE_SV xmvlog:*E,EXPSMC for array.size() usage during solve in constraint
AVSREQ-192295 LP_1801 Xcelium report UPFERRM when using traverse_macros command and upf version 3.1 / 2.1
AVSREQ-192332 SIM_PERFORMANCE perf_analysis wrongly reporting missing newperf/plusperf
AVSREQ-192368 SPECTRE_AMSD Build crash with nightly debug kit
AVSREQ-192395 LP_1801 [MTK-LPS] Xcelium return supply_on / supply_off value mismatch IEEE standard
AVSREQ-192399 SV_PERFORMANCE Sim memory degradation seen with 23.04-a RC kit as compared to 23.03-a release
AVSREQ-192451 DEBUG_DESIGN_DATABASE xcelium.d directory contains sys.d soft link instead of run.d soft link
AVSREQ-192462 SIM_SV_VHDL Print module name of instance (without a definition) using tcl even though module definition does not exist
AVSREQ-192475 SIM_PERFORMANCE 1.78X elaboration performance degradation due to deadcode optimisation
AVSREQ-192482 DMS_PERF EEnet performance is slow when using built-in EE_pkg libraries
AVSREQ-192522 CORE_RAND Rename dist histogram report from index.html to distreport.html
AVSREQ-192547 CORE_RAND Sort data from HCS for dist analyzer reports
AVSREQ-192575 SV_CODEGEN INTERR xmvlog_cg ivia_pair_sanity_check - vst and ot mismatch at line 14522 for vst class: 557
AVSREQ-192600 SPECMAN_ERRORS need to update WARN_NO_VM_FOR_VSOF_FILE content from Emanager to Vmanager
AVSREQ-192604 SPECTRE_AMSD Analog error when using probe -flow - INTERR, INTERNAL EXCEPTION
AVSREQ-192643 SV_CODEGEN CM Block got HANG in Simulation stage with ENABLE_RSWT_RDWO
AVSREQ-192672 ELAB_PERF Request for LWD generation performance enhancement
AVSREQ-192691 SIM_PERFORMANCE xmsim *F,INTERR when probing: vxt_val_function_call
AVSREQ-192742 PARSE_SV Need vector bit support for *E,PCRFNC
AVSREQ-192767 SV_CODEGEN Code Gen crash issue in IRC BLOCK
AVSREQ-192793 SPECMAN_COV Coverage Callback "null access" issue in is_item_sampled()
AVSREQ-192812 SIM_SV xmsim does not provide an error message when the error happens during __run_exit_handlers
AVSREQ-192837 LP_1801 [MTK-LPS] Xcelium needs to support get_supply_on_state
AVSREQ-192885 DEBUG_DESIGN_DATABASE Cannot trace drivers from the output VDD from macro
AVSREQ-192891 LP_1801 simulation difference between 21.09.v004 and 22.03.v008 in driver in interface
AVSREQ-192906 SIM_PERFORMANCE INTERR during ida_probe
AVSREQ-192920 DMS_ELAB add an option -dms_rnminfo_d
AVSREQ-192939 ELAB_BIND Tool crash while using -showcudep switch
AVSREQ-193040 PARSE_SV Xcelium tool Crash with IWB user code
AVSREQ-193041 VST_PRIME Xmelab crash seen for customer -SM block on 23.04-aRC Kit with options "-xform_lite Named_conn_udp" & "-xform_lite Reg_clock_xform"
AVSREQ-193056 SV_INTERFACE Build crash with nightly debug kit - MESSAGE: cu_vifc_check_access - unmark flags mismatched
AVSREQ-193060 XM_UTILS_GENERAL xmls -source is crashing
AVSREQ-193075 PARSE_SV Compiler does not resolve methods inherited from parameterized type
AVSREQ-193078 ASSERTION_SVA Got *E,ASRTST when using implication property with ##0
AVSREQ-193082 FUNC_SAFETY_CONCURRENT mismatch between serial/concurrent engine
AVSREQ-193118 SIM_PERFORMANCE Elaboration crash with cu_qualify_fanout_to_sps message
AVSREQ-193141 LP_1801 Do not extract by default text-refs for element list in the UPF commands file
AVSREQ-193206 VPI_GENERAL Xcelium crashing when using VPI cbRelease with UPF
AVSREQ-193218 DEBUG_PROBE Invalid write in IndagoExecuteIdaProbeCmd
AVSREQ-193273 PARSE_SV xmvlog: *E,SVNOTY when migration from VCS to Xcelium
AVSREQ-193311 RAND_SOLVER F,RNDCHKRF Randomization Checker Failure during randomize call
AVSREQ-193325 LP_1801 [LPS] xmelab crash with "MESSAGE: apx - can't abstract pointer"
AVSREQ-193336 DMS_SOLUTIONS Ability to start and stop profiling at a given specified time
AVSREQ-193337 LP_1801 xmelab:*SE,EMTELE with member of packed struct as port in find_object
AVSREQ-193346 SR_XEML Lag between LSF job submission
AVSREQ-193360 SIM_SV Usage of $size and $dimension operators differ from other simulators
AVSREQ-193365 DMS_SOLUTIONS Create a 'cdsinfo.tag' file in each of the 5x libraries delivered with an XCELIUM build
AVSREQ-193423 DEBUG_DESIGN_DATABASE Statically link protobuf into libsagegen
AVSREQ-193431 LP_SIM_PERF Fix performance issue in ssl_pwr_chk_link
AVSREQ-193556 ELAB_SV elab crash while working on AVSREQ-188850
AVSREQ-193557 SIM_PERFORMANCE Xmclone simulation overhead – Deadcode optimization not kicking in
AVSREQ-193600 SIM_PERFORMANCE xmelab *F,INTERR in MSIE: cu_ltw_early_sanity_check
AVSREQ-193602 SV_CODEGEN Xcelium reports internal exception during code generation
AVSREQ-193668 COVERAGE_CODE Covered FCC expression coverage showed as uncovered
AVSREQ-193679 POWERPLAYBACK_GENERAL PPB mapping failed issue due to backslash "\" in 2-dimensional array's name
AVSREQ-193685 DMS_AMSD Using ie_card.scs file and a generate statement causes the error *E,TYCMPAT due to difference in coercion behaviour
AVSREQ-193689 SPECTRE_AMSD AMSD: Hier_DVS: SpectreX Montecarlo - Simulation complete via $finish(1) at time 0 FS + 17 [L2E_2_dynsup.vams:179]
AVSREQ-193703 ELAB_SV Virtual Interfaces are wrongly getting bypassed during static analysis flow.
AVSREQ-193718 SR_XEML New job dispatch system complains job array index too large
AVSREQ-193745 SV_INTERFACE xmelab: *E,CUIMBC with interface modport
AVSREQ-193754 LP_1801 A xcelium lp command leads IXCOM instruments invoking twice and makes fatal error
AVSREQ-193772 ELAB_BIND Elab hang for LP simulations with 22.09 & 23.03 , passes with 22.03
AVSREQ-193806 LP_1801 literals connected to PA models are NOT corrupted when driving PD is OFF when is_analog
AVSREQ-193854 PARSE_SV Likely wrong xmvlog NOUNAD warning
AVSREQ-193937 DEBUG_DESIGN_DATABASE Encrypt persistent files
AVSREQ-193941 DEBUG_DESIGN_DATABASE Record connect supply net info to SQL database
AVSREQ-193947 LP_1801 ignore upf power switch if the powerswitch is part of GL netlist
AVSREQ-193981 FUNC_SAFETY_SIM *F,INTERNAL EXCEPTION seen in fault concurrent simulation
AVSREQ-194070 FUNC_SAFETY_ELAB Xmelab Internal Error sslu_ascend_helper - null ipp
AVSREQ-194091 SIM_VHDL CLONE - T(0): sv_seghandler - trapno -1 addr((nil))
AVSREQ-194147 SIM_PERFORMANCE Using new switches for latch pruning in non-xprop build gives xmelab crash
AVSREQ-194161 SIM_USABILITY Follow up issue on AVSREQ-178911 (error message when simlogsize is reached is not parsable)
AVSREQ-194171 VST_PRIME Dot star mixed port connections transform
AVSREQ-194172 PARSE_SV [DCSG-SOC] xmvlog: *E,ILLCSR [while migrating to Xcelium]
AVSREQ-194177 PARSE_SV Missing textrefs for index and signal of interface referenced in macro within generate statement
AVSREQ-194220 IXCOM MESSAGE: sv_seghandler - trapno -1 addr(0x2acd6d0e0be8)
AVSREQ-194272 SIM_PERFORMANCE CA entries from hdr files in 23.03.v001
AVSREQ-194273 GLS_GENERAL xmelab internal exception with Illegal writer – cag_get_driving_expr when -access +r
AVSREQ-194281 SIM_RACEDT Print the hierarchy in race detect warning message with only instance name
AVSREQ-194391 SIM_VHPI Cocotb end of simulation crash
AVSREQ-194393 PARSE_SV xmvlog INTERR vst_datatype() - invalid class with -allow_match_backref_string_builtins
AVSREQ-194395 FUNC_SAFETY_CONCURRENT Concurrent Fault Sim Internal Error 23.03s2 sv_seghandler
AVSREQ-194425 LP_1801 [MTK-LPS] Xcelium simulated signal value is different inside / outside the isolation cell
AVSREQ-194426 SPECTRE_AMSD Overriding a string parameter by concatenating multiple strings together gives fatal error
AVSREQ-194428 SPECTRE_AMSD Overriding a string parameter by a field out of a string array gives xmsim error
AVSREQ-194457 MSIE_ELAB Long incremental elaboration in multi-step MSIE
AVSREQ-194458 FUNC_SAFETY_XFSG xfsg not generating extracted fault list in FCM for default transient sync event flow
AVSREQ-194467 SIM_PERFORMANCE xmsim *F,INTERR sigsegv: xdiDataTypeFcty::FindOrCreateObj
AVSREQ-194499 SIM_PERFORMANCE Primary elaboration crash cuv_handle_trdrv_share_flag - unexpected nettmp kind - nettmp_intdst
AVSREQ-194587 XPROPAGATION_GENERAL Unexpected X with -enable_xp_clk_x_trigger
AVSREQ-194588 SV_DATATYPES Unexpected Xcelium behavior with -allow_match_backref_string_builtins
AVSREQ-194592 SV_CLASSES Elaboration is hanging while running build.
AVSREQ-194595 FUNC_SAFETY ProcessFanoutSerial crash with -fault_outport_mixload option in serial
AVSREQ-194632 LP_MSIE Xcelium crashes with Low power simulations at elaboration stage
AVSREQ-194634 XRUN_GENERAL Follow-up issue on SCCLNG description not in sync with the tool installation versions
AVSREQ-194661 SV_CODEGEN [Customer:PCIE(Full-Chip)] systf_sformatf_vfms_cnfms library function consuming 60% in one of the profile entry
AVSREQ-194672 SIM_PERFORMANCE Build is crashing with 'cu_expr_has_dyndrv - unexpected type 595' message when xmclone is enabled
AVSREQ-194681 XPROPAGATION_GENERAL xprop fail in CAT and pass with FOX
AVSREQ-194720 COVERAGE_INTERFACES coverage with duplicate bins
AVSREQ-194773 XPROPAGATION_GENERAL Xprop Issue due to switch in low power
AVSREQ-194785 ELAB_SV CONOTR warning for clocking block output read in a foreach expression
AVSREQ-194807 DEBUG_DESIGN_DATABASE Displays incorrect active driver
AVSREQ-194825 DMS_SIM Initialize ft_time64
AVSREQ-194859 ASSERTION_PERFORMANCE Assertion optimization with -ABVSVADISABLE2009 and SVFs in disable iff
AVSREQ-194886 SIM_PERFORMANCE Internal exception with message "dto_range_width" on using -bbinst with -bbconnect
AVSREQ-194893 SPECMAN_INTEF Internal error at assertion call-back registration using encrypted module
AVSREQ-194930 SV_PARAMETERS xmelab: *F,INTERR: vsto_ots_pdata -illegal flags, class 516
AVSREQ-194936 SIM_PERFORMANCE Crash is reported while primary elaboration if afile is provided but with access rwc there is no crash
AVSREQ-194942 SIM_PERFORMANCE MESSAGE: cu_qualify_fanout_to_sps: xsps_1 == xsps_2. Option -disable_super_prune_opt can be tried as workaround.
AVSREQ-194952 SIM_PERFORMANCE Primary build crash sv_seghandler - trapno -1 addr
AVSREQ-194979 ASSERTION_SIM Incorrect behavior of $assertoff for deferred assertions
AVSREQ-195000 ELAB_CLONE Support tran HDC scenario with xmclone
AVSREQ-195004 LP_1801 Xcelium doesn't issue error on a missing "$" of path variable for UPF
AVSREQ-195031 SV_PARAMETERS intermittent xmelab crash - vsto_ots_pdata - illegal flags, class 516
AVSREQ-195145 DEBUG_DESIGN_DATABASE Wrong string parameter value with LWD
AVSREQ-195159 IP_PROTECT_GENERAL LEVEL1AUTOPROTECT when using `ifdef ~`else ~ `endif for IO ports
AVSREQ-195200 COVERAGE_COVERGROUP xmelab: *E,CGDSVI - Hierarchical access of covergroup instance through virtual interface is not allowed.
AVSREQ-195201 LP_1801 *E,UDFUOBJ: [LPS] No IEEE 1801 object is found for SV_LOGIC2UPF_MD
AVSREQ-195209 XM_UTILS_GENERAL XMUTILS mirroring does not work without access
AVSREQ-195212 XM_UTILS_GENERAL XMUTILS does not support objects within the protected scopes
AVSREQ-195215 LP_ISOLATION set_isolation -source does not work with power domains
AVSREQ-195247 DEBUG_DESIGN_DATABASE Reinvoke and keep parent process alive to avoid GUI being terminated by DRM
AVSREQ-195248 DEBUG_DESIGN_DATABASE Reinvoke exits Verisium Debug unexpectedly
AVSREQ-195253 GLS_GENERAL Illegal writer – cag_get_driving_expr (VST_D_INSTANCE)
AVSREQ-195254 VST_PRIME GLS internal error with xform_lite udp_wrapper_inst_to_udp_inst
AVSREQ-195264 ELAB_SV Closed loop deadcoding is required to be implemented in Static Analysis flow
AVSREQ-195280 LP_1801 Crash in lps with MESSAGE: pwr_alias_nconn: inconsistent tid!
AVSREQ-195304 LP_1801 Power domain is not corrupted even when the primary power is turned off
AVSREQ-195355 DMS_LP_AMS [UPF PARTL AMS] VCT is not taking effect on electrical supply and ground signals
AVSREQ-195382 DEBUG_DESIGN_DATABASE Intermittent DLREAD and INTERR in xmelab with -lwdgen
AVSREQ-195407 SIM_RACEDT Option to report glitches for specified signals
AVSREQ-195437 VWDB py-API 'value_at_time' does not return the value of a signal.
AVSREQ-195459 LP_1801 Requesting help on generation of .bind_checker directory and understanding wrong line number
AVSREQ-195462 DEBUG_DESIGN_DATABASE Unexpected VHPI NOTOTO when doing driver tracing on vhdl variable
AVSREQ-195474 ELAB_SV MULAXX multidriver error not accounting for independent elements/bits of a variable
AVSREQ-195494 DEBUG_DESIGN_DATABASE "-lwdgen" causing elaboration time degradation
AVSREQ-195508 SPECMAN_E uvm_configure fails accessing field defined within a subtype
AVSREQ-195607 LP_1801 [Customer-LPS] Xcelium need to support force between VHDL and SV
AVSREQ-195706 LP_1801 PA Elaboration crash vst_identifier () - bad class
AVSREQ-195747 LP_1801 link_driver_sim_state driver is const from liberty interface
AVSREQ-195781 LP_1801 Members of struct are not searched by 'find_objects'
AVSREQ-195825 FUNC_SAFETY_CONCURRENT [*E,UNSUSF] Unsupported System task/function $feof in constant context.
AVSREQ-195828 XRUN_GENERAL xrun: E:BDOPTQ: Unknown option "-afile something"
AVSREQ-195929 LP_VHDL -lps_ft_graph is not default when compiling VHDL code with xrun but using makelib/endlib
AVSREQ-195945 LP_1801 PCOERC error observed even in the non-lp run.
AVSREQ-195977 LP_1801 [LPS] Xcelium need to execute always block when power is turned from OFF to ON
AVSREQ-195997 SIM_PERFORMANCE dead pib optimizations has 5% overhead at build time
AVSREQ-196003 SPECMAN_GENERAL random crash due to inconsistency error in compiled mode.
AVSREQ-196004 SV_PORTS Internal Error flagged during SDF back annotation
AVSREQ-196028 SV_DPI Archive file (.a) not being loaded and causing F,NOFDPI error
AVSREQ-196048 GLS_GENERAL Getting this error during gate level simulation. xmsim: *E,SST2ER: SST2 interface error: Invalid control value.
AVSREQ-196064 RAND_SOLVER Randomization call unexpectedly succeeds
AVSREQ-196104 DMS_SIM Port the fix for AVSREQ-183131 to Xcelium Green
AVSREQ-196130 SR_XEML XEML should die if it can't find liblsf.so
AVSREQ-196134 SV_PERF With coverage + Cadence VIP the testcase is running for more than 2 days
AVSREQ-196202 COVERAGE_INTERFACES Contribution run for all engines (formal) - coverage library support
AVSREQ-196275 SYSC_COMPILER Makefile.xmsc error due "=" not being converted to $(equal_to_sign_variable) in xmsc_xm_main_object.o rule
AVSREQ-196276 JUPITER_ENGINE requirements on 'MCE can't get 100% ….' messages printing
AVSREQ-196280 ELAB_BIND Package not imported is getting elaborated
AVSREQ-196303 JUPITER_ENGINE XLM MC run slower with -initreg0
AVSREQ-196304 MSIE_ELAB LWD generation for MSIE (related to DSSVAR/DSSUSZ issue - AVSREQ-194209)
AVSREQ-196343 XPROPAGATION_PERFORMANCE Skip pot traversal that transfers xprop information to vhdl processes in non-VHDL designs
AVSREQ-196355 SV_CG_PERF wall time randomly 3x high on a checkpoint
AVSREQ-196362 ELAB_CLONE Xmclone running into TRAN issues
AVSREQ-196367 VST_PRIME WIDERR in 23.05 release with -XFORM_LITE prod option
AVSREQ-196369 SIM_PERFORMANCE Xprop build time has increased in new kit
AVSREQ-196420 COVERAGE_CODE illegal IGN is shown with FCC/set_com
AVSREQ-196424 ELAB_SV Enclosed task/functions are getting considered as recursive in static analysis flow.
AVSREQ-196465 LP_BUILD_PERF xrio build performance
AVSREQ-196493 PARSE_SV *F,INTERR Internal error 23.07 Nightly AGILE
AVSREQ-196569 SIMVISION_GENERAL Add a Warning when Invoking simvision alongside setting $INDAGO_ROOT/$VERISIUM_DEBUG_ROOT
AVSREQ-196576 MSIE_ELAB Educate msie genhref skip clones for doic1 , dolms, doaccess checkpoints in DSS and AutoMSIE flows
AVSREQ-196624 ELAB_PERF productize the -enable_skip_if_hash_remove option
AVSREQ-196634 VST_PRIME XFORM_LITE For_generate_always_01 leads to SCWNPO elaboration error
AVSREQ-196635 SPECTRE_AMSD Customer faces analog elaboration fail
AVSREQ-196640 PARSE_SV Textref is missing for uvm_macro inside generate statement
AVSREQ-196643 GLS_GENERAL Xcelium is not able to dump SHM, VWDB, or FSDB
AVSREQ-196667 SIM_PERFORMANCE GLS SCAN function simulation performance compared to competitors
AVSREQ-196685 SV_PERF Higher contribution of clocking block in simulation
AVSREQ-196707 PROFILER_XPROF Simulation memory profile run failed with internal exception
AVSREQ-196753 LP_LIBERTY New Flow: ANSI style declaration issue
AVSREQ-196759 CORE_RAND Xcelium asynchronous reset behavior is different
AVSREQ-196769 SV_PERFORMANCE Vector pointer argument caching needs to be extended for non-leaf task/ functions
AVSREQ-196829 RAND_SOLVER RNDREJ: array index out of bounds warning with latest releases 23.06
AVSREQ-196855 VST_PRIME 23.06 Xcelium Agile: xmelab: *E,WIDERR: Indexed part-select width is less than or equal to zero
AVSREQ-196864 SV_PERFORMANCE DCSG [IOA] FPA Block Elaboration Crash issue
AVSREQ-196879 XM_UTILS_GENERAL xmls -source is crashing for AST [Follows AVSREQ-193060]
AVSREQ-196915 SIM_PERFORMANCE elab crash with single xrun msie (23.03.v001) workaround -disable_local_share_ca_build -disable_ca_share_opt -nocalocalopt
AVSREQ-197003 GLS_GENERAL Getting elaboration error when using newer version.
AVSREQ-197023 SR_BACKDOOR -xceligen backdoor_output_file crashes
AVSREQ-197030 SR_BACKDOOR using -ml and -xceligen backdoor_output_file gives an error on empty backdoor_trace.txt
AVSREQ-197032 SR_BACKDOOR Using -xceligen backdoor_output_file= with non-existent directory silently fails
AVSREQ-197089 MSIE_SIMULATION Introduce error on simulation when any of the MSIE loaded primary snapshots are built with href wild cards
AVSREQ-197090 PROFILER_SIM_RUNTIME Introduce a warning in xmprof.out telling that the MSIE primary snapshot is built with HREF wild card
AVSREQ-197121 SYSC_GENERAL Base class vcd_trace defined inside sc_vcd_trace.h is under #if 0
AVSREQ-197155 SIMVISION_MS SimvisionMS: Browse Currents - Inconsistency in the way browse currents table is displayed after changing the sort mode when sorting by real values
AVSREQ-197170 ELAB_SV Static analyzer is required to be enabled with -ENABLE_BIND_WITH_COMMON_PKG
AVSREQ-197209 SIM_PERFORMANCE Crash seen in VTW flow '-disable_share_ca_build
AVSREQ-197237 LP_1801 UPF: make "-define UPF_PKG_DEBUG" default
AVSREQ-197243 SV_INTERFACE VIFUCON error should be a simulation error instead of elaboration if class is unused
AVSREQ-197254 SV_DPI Support for shortreal open array in DPI import
AVSREQ-197270 SIMVISION_MS SimvisionMS: Terminals ending in lower case in the Browse Currents are not highlighted in the schematic tracer
AVSREQ-197273 ELAB_SV Simulation internal error in customer design due to task/ function deadcoding
AVSREQ-197301 LP_1801 xmelab: *N,FOOESR: [LPS] The find_objects command returns no objects
AVSREQ-197333 VHDL_GENERAL difference in handling of line type between 2109 and 2303
AVSREQ-197364 UVM_REG File cdns_uvmreg_utils_pkg.sv is corrupted in Xcelium install
AVSREQ-197385 POWERPLAYBACK_GENERAL Support an alternate copy of the "libdac.so" to read VWDB/SHM for PowerPlayback
AVSREQ-197407 SV_CODEGEN xmvlog_cg crash "too many preds"
AVSREQ-197415 SIM_PERFORMANCE Internal exception . MESSAGE: gwm_filter - CUV_NL default (281).
AVSREQ-197444 MSIE_ELAB xmls -module is missing modules in MSIE multi step flow
AVSREQ-197506 XRUN_GENERAL xrun -file is not working when file has -v option
AVSREQ-197569 DEBUG_DESIGN_DATABASE Crash with MESSAGE: bad path passed - spath_simplify_nostat
AVSREQ-197637 DEBUG_DESIGN_DATABASE Internal exception when enable debug_opts verisium_interactive
AVSREQ-197665 SPECMAN_SAVE_RESTORE Copy error with save/restore in VCS 14->20
AVSREQ-197667 PARSE_SV With autofetch the paths shown in the simulation logs are not relative to simulation dir
AVSREQ-197674 COVERAGE_TOGGLE Some clock signals toggle coverage is shown as uncovered when coverage is reset at end of the reset cycle
AVSREQ-197678 DMS_ELAB Add option to allow hierarchy in connect modules
AVSREQ-197686 LP_1801 UPF: Repeater strategy showing *SE,ISOPLCE Output isolation cannot be placed at the port ./../foo. Misleading soft error and port is there in the design
AVSREQ-197687 LP_1801 UPF: nested struct causing "NOHRPTH" soft error for Iso and Ret Strategy
AVSREQ-197769 SPECTRE_AMSD AMSD: Seeing assertion failure during simulation on call to $cgav. Occurs from XM 22.09-s005
AVSREQ-197882 JUPITER_BRIDGE Elaboration crash during ATPG sim using multi-core ( MESSAGE: Cannot have net fanout with a non talking ACC driver)
AVSREQ-197899 GLS_GENERAL internal exception upon elaboration : Illegal writer – cag_get_driving_expr
AVSREQ-197965 SV_CLASSES xmelab hang on 22.09v, not on 23.03.v002
AVSREQ-197966 MCS_DEV Crash in secondary simulation due to uninitialized TRDRV
AVSREQ-198069 MSIE_ELAB False *W,DSSSIZ reported for '0 on MSIE boundary
AVSREQ-198124 DEBUG_DESIGN_DATABASE Simvision FSM windows display nothing-FSM states using typedef enum
AVSREQ-198159 PARSE_SV xmvlog: *E,NOFUN1 Illegal operand of void'().
AVSREQ-198224 XRUN_GENERAL xrun -R overrides the user defined -ahdllibdir
AVSREQ-198225 VHDL_GENERAL Change representation of the VHDL generate block name
AVSREQ-198233 SIM_PERFORMANCE Xcelium asynchronous reset behavior is different with / without noprune
AVSREQ-198292 GLS_PERFORMANCE track update for new latch to be used in clock gator circuits
AVSREQ-198293 PARSE_SV Xcelium exits unexpectedly when FSDB is being dumped
AVSREQ-198316 SPECMAN_E sequences - show do queue command
AVSREQ-198338 COVERAGE_PERFORMANCE LTC bench coverage build time is 1.6x longer (than no coverage build)
AVSREQ-198347 SV_GENERAL SmartLog missing xm_force message and xm_release message
AVSREQ-198387 LP_1801 Fix crash with disable bindaon opt
AVSREQ-198402 MSIE_ELAB INTERR in MSIE build since 2209v5
AVSREQ-198557 PARSE_SV Some macros are unexpandable with -autofetch
AVSREQ-198566 PARSE_PERF Remove blank lines from xrun.log file after each entry of cuscope declaration with -parseinfo cuscope/cuscope_verbose
AVSREQ-198593 DEBUG_DESIGN_DATABASE Provide API to XLM LP team to record UPF commands file to SQL LWD
AVSREQ-198787 DEBUG_DESIGN_DATABASE Multiple dsn files generated when build with -lwd_prepare/-lwd_complete done in the same directory
AVSREQ-198842 LP_1801 change default direction of Liberty internal_power / internal_ground to output
AVSREQ-198972 PARSE_SV [LPS] Xcelium reports DUPIND error
AVSREQ-198990 SV_PARAMETERS Unresolved parameter due to its usage in an illegal context.
AVSREQ-199000 POWERPLAYBACK_GENERAL Power Playback need an option to dump mapping rate log in the simulation directory
AVSREQ-199030 DMS_SIM force X/Z on real variable using Tcl
AVSREQ-199031 DOCUMENTATION Enhancement for Integrated Coverage User Guide
AVSREQ-199078 SPECTRE_AMSD AMS: 32'(logicBus) is not supported during esimPublishing
AVSREQ-199161 XPROPAGATION_GENERAL Crash with latest agile in customer's design with message: vsto_ots_flags - class, class 592
AVSREQ-199181 ELAB_BIND Elaboration crash after new 23.03.v003 RC kit
AVSREQ-199311 SIM_PERFORMANCE 23.07 RC kit is showing long simulation time for xprop
AVSREQ-199328 VHDL_CODEGEN Customer is running into interr when using unconstrained array as a port.
AVSREQ-199345 SR_XEML XEML fails to launch jobs unless '.' is in the path
AVSREQ-199449 SV_INTERFACE Intermittent crash with message sslu_ascend_helper - climb out of Vlog when xmclone is used
AVSREQ-199454 ASSERTION_SVF xmvlog fatal error - xut_otid_to_formal_lookup
AVSREQ-199463 SIM_PERFORMANCE Incorrect simulation results due to gprune optimization
AVSREQ-199496 LP_LIBERTY *E,NOPORT error on models without any data/pg port
AVSREQ-199503 SIM_VHDL vhdl process not re-exercised without -linedebug option
AVSREQ-199553 SV_PARAMETERS xmelab: *E,NOTDOT (./tc.sv,9|315): Hierarchical name ('mem_ds_non_p2p_ord_req_to_dpram.waddr') not allowed within a constant expression [4(IEEE)].
AVSREQ-199647 SAVE_RESTART_DMTCP Tool to determine PBSR performance
AVSREQ-199648 SR_BACKDOOR Xcelium ML doesn't consume licenses in control mode if no constraints are imposed by the backdoor
AVSREQ-199758 LP_1801 [LPS] Initialize un-driven supply_net_type input ports to 0
AVSREQ-199798 LP_1801 *F,SZTOLG is faced only in Power-Aware Simulation
AVSREQ-199923 MSIE_ELAB Partitioner takes huge time, option -XMSIE_EXCLUDE_DEFPARAMS needed with -automsie
AVSREQ-199936 SIM_PERFORMANCE Xcelium simulation result is different with / without newperf option
AVSREQ-199963 LP_1801 crash in elaboration
AVSREQ-199976 LP_1801 Add support to disable assertion control with -lib_model
AVSREQ-200030 DEBUG_DESIGN_DATABASE xmelab INTERR: compress_bub_read() - The buffer dest was not large enough to hold the uncompressed data.
AVSREQ-200052 SR_BACKDOOR backdoor_trace.txt compilation does not happen with -xceligen backdoor_output_file=
AVSREQ-200064 ELAB_SV Need support of unhandled nodes during static analysis
AVSREQ-200116 ELAB_SV Support of Always block in dynamic stuck at value computation
AVSREQ-200158 VST_PRIME GPU blocks (live design) got stuck during Xmelab for 23.08 nightly
AVSREQ-200182 GLS_TIMING Partial wildcard matching support
AVSREQ-200187 VST_PRIME Elab Crash seen for one of the core of CPU blocks with 23.08 nightly kit
AVSREQ-200196 ELAB_SV Virtual Interface normalization needs to be enhanced for dynamic stuck at value computations
AVSREQ-200415 MSIE_ELAB Enable relaxation of DSSVAR/DSSUSZ errors for snapshot generation and loading only
AVSREQ-200437 LP_1801 Zero delay loop is causing a stall in the simulation
AVSREQ-200442 VST_PRIME Elab Crash seen for GPU blocks with 23.08 nightly : sv_seghandler - trapno -1 addr(0x15519764c0c8)
AVSREQ-200740 DEBUG_DESIGN_DATABASE xmelab INTERNAL ERROR 'rlfunc unknown wad struct id 'ifs_cod' PTR'
AVSREQ-200875 GLS_GENERAL Elaboration time *F,INTERR: INTERNAL ERROR: Xcelium tool (22.09) when compilation option "-vlogcontrolrelax CUILLHIN" or "-plussv" is passed
AVSREQ-201141 LP_1801 elaboration exits unexpectedly with MESSAGE: pwrCrossCheckRtnObjects_self
AVSREQ-201190 SIM_PERFORMANCE NBA assignment not getting updated due to -enable_prune_reg_always_opt
AVSREQ-203346 DEBUG_DESIGN_DATABASE Clear PSD when -disable_persistent_sources_debug is used
AVSREQ-79023 PARSE_SV BIMNCN - support for builtin enum functions .num and .first
AVSREQ-82139 PARSE_SV Nested macro issue
AVSREQ-88754 PARSE_SV E,EXPSMC for using array.size() in constraint
AVSREQ-92340 PARSE_SV INTERR: xmvlog_cg: tl_val_offset - wire is invalid
AVSREQ-92750 SV_GENERAL enum methods not supported in parameter - BIMNCN
AVSREQ-92851 PARSE_SV "Invocation of built-in methods in constant expressions is not yet supported."
AVSREQ-93038 SV_GENERAL xmvlog: *E,BIMNCN (test.sv,50|39): Invocation of built-in methods in constant expressions is not yet supported. [SystemV]
AVSREQ-98451 SV_GENERAL SV invocation of built-in methods in constant expressions is not yet supported
AVSREQ-98750 DMS_SVAMS Add support to support nettypes through switch primitives – tran, tranif0, tranif1 (*E,CUVINP errors)
AVSREQ-99868 PARSE_SV ncvlog: *E,BIMNCN : IUS SystemVerilog parsing issue .first enumerated method in module parameter definition
AVSREQ-99963 SYSC_GENERAL Cannot connect SystemC double ports on SV real ports: fatal error or tool crash at elaboration

October, 2023

AVSREQ-176117 SPECTRE_AMSD parameterize vsup of ie card with AXUM use-model
AVSREQ-197584 VPI_GENERAL Enhance vpi force callback for individual members of packed structs
AVSREQ-200635 LP_SIM_PERF elab exits unexpectedly finalize_vhdl_net LPS build - due to en_vaca_opt
AVSREQ-201590 LP_SIM_PERF Unexpected tool exit seen in 2303v003 related to en_vaca_opt
AVSREQ-201815 SIM_SV End of simulation log not present in smartlog
AVSREQ-201994 DMS_LP_AMS Error with negative supplies in non-VCT UPF+AMS flow
AVSREQ-202631 DMS_LP_AMS LPMSSN warning in 23.09.v001 (only when -xrio option is used)
AVSREQ-203105 LP_SIM_PERF xmelab: *F INTERNAL EXCEPTION - sv_seghandler - trapno -1 addr((nil))
AVSREQ-203156 DEBUG_DESIGN_DATABASE Design stops responding at "Parallel LWD Data Generation" when "-lwdgen" is in Xrun option list
AVSREQ-203203 DEBUG_DESIGN_DATABASE Struct inside a generate for loop is missing textref in Verisium Debug Source Browser
AVSREQ-203564 SYSC_GENERAL Coverage support for gcc/g++ compiled code
AVSREQ-204207 DOCUMENTATION Fix constraint analyzer references
AVSREQ-204297 SPECMAN_E undefined symbol: var_opt_core_in_command_line

November, 2023

AVSREQ-176117 SPECTRE_AMSD parameterize vsup of ie card with AXUM use-model
AVSREQ-187679 PARSE_SV EXPLPA error when creating var
AVSREQ-192605 LP_ISOLATION Implementation of the full -no_isolation semantics for path-based analysis
AVSREQ-196329 PARSE_SV Error with variable declaration
AVSREQ-200454 DEBUG_COMMAND xmsim: *F,IDAIND: Could not find location of Indago installation "" ""
AVSREQ-200914 SIM_VHPI VHDL elsif / else not showing the generate hierarchies in Simvision
AVSREQ-201994 DMS_LP_AMS Error with negative supplies in non-VCT UPF+AMS flow
AVSREQ-202729 IP_PROTECT_GENERAL MESSAGE: Unexpected signal #11, program terminated (null)
AVSREQ-203156 DEBUG_DESIGN_DATABASE Design stops responding at "Parallel LWD Data Generation" when "-lwdgen" is in Xrun option list
AVSREQ-203423 VPI_LWD vpiEnumNet should not access vpiRange
AVSREQ-204307 DMS_ELAB Elaboration exits unexpectedly with SV Bind on Spice
AVSREQ-204896 LP_1801 *SE,ILLOBJU is reported for an argument of "-model" option in UPF command "set_port_attributes … -is_analog"
AVSREQ-205232 VPI_GENERAL Add support for unpacked struct wire port
AVSREQ-205761 DMS_ELAB add -dms_real_net_init as part of xrun -help

November, 2023

Cadence's Xcelium Logic Simulation provides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments. Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles. Xcelium is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.

Accelerating DFT Simulations with Xcelium Multi-Core

Are long DFT simulations posing a big challenge to meet your tight project schedules? We have a solution to accelerate the long running DFT tests. Watch this video to know how easy it is to set-up Xcelium Multi-Core to get up to 5X acceleration for a variety of DFT use cases ranging from serial and parallel ATPG to MBIST and LBIST
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.

Owner: Cadence
Product Name: XCELIUM
Version: 23.09.003 (XCELIUMMAIN) *
Supported Architectures: x86_64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Linux **
Size: 14.6 Gb


Cadence XCELIUM 23.09.003

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Cadence XCELIUM 23.09.003