Cadence SSV Release Version 21.16.000
Cadence SSV Release Version 21.16.000 | 43.5 Gb
The SSV Release Team has unveiled the Cadence Silicon Signoff and Verification (SSV) 21.10.000. This solution encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout.
Featured Enhancements
Here is a list of some of the important updates made to Tempus Timing Signoff Solution and VoltusTM IC Power Integrity Solution for the 21.1 production release
Tempus
New Tempus Licenses
The following new licenses have been added in Tempus:
- 3nm option: Tempus Timing Signoff Solution 3nm Option
- Advanced Analysis option: Tempus Advanced Analysis Option
Set Instance Library Flow
The Tempus software has been enhanced to support instance-level library assignments. With this new flow, the software binds the user-specified library to instances, and overrides the tool’s default library binding mechanism. You can revert to default library binding by using the corresponding reset command.
Voltus
Extreme Modeling Flow Enhanced
The Extreme Modeling (XM) flow has been improved to generate context-independent power-grid view (xPGV) models. This flow has the ability to dynamically create xPGV models for only those IP blocks of the design that a user wants to analyze.
The key capabilities of the new XM model are:
- accurately capture chip-level RC parasitics and demand current
- run your largest designs much faster with lower memory
- reuse IP models in different designs or for multiple instantiations within a design
Support for User-Defined Power Targets
The State-Propagation-Based Vectorless flow now supports specification of user-defined power targets for full-chip power analysis in the XP mode. You can specify the power targets for full chip, physical block, logical block, and power net. When these targets are specified, Voltus will automatically scale the toggle rates of clock gate ratio, input, macro, and sequential activities to meet the specified power targets.
New Command to Trim Cell Libraries
A new command, trim_pg_library, has been added that enables you to remove a cell or a list of cells from a cell library. This command allows you to trim the size of a cell library by removing unwanted cells, which can reduce the overall time required for extraction.
Ability to Display Temperature Maps in GUI
Voltus GUI has been enhanced to display hierarchical temperature maps using the configuration file and the hierarchical layer-based temperature files generated by Celsius (system-level thermal analysis tool). When these files are specified, you can view the tile-based temperature distribution for each layer of the chip.
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Fixed CCRs in Tempus 21.10 RTM
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2452798 Incorrect minimum rise delay reported
2447608 IMPESI-3194 errors in PGV flow
2443803 Stylus Tempus DSTA uses Legacy UI command when running in CUI mode "-distributed -stylus -wait 20 -cpus 2 -nowin"
2442861 High run time with Tempus leakage ECO with low fix rate and .summary file not getting dumped
2440312 apply_boundary_model_constraints does not accept a "-" in the bus bundle name
2434416 set_cdb_binding is not logged in the logv/cmd file
2434398 Larger than expected run time increase of bus over nobus run
2429552 Paths go unconstrained inconsistently in C-MMMC
2429475 Tempus eco_opt_design -power degrades setup time
2421061 set_disable_timing not working on library cell arc and not throwing any error
2417838 Give info message when reading in constraints from boundary model
2413011 Boundary model should not save annotated glitch for TAIgnored nets
2408473 Attribute mapping load_pins to leaf_load of net type not working in DSTA compared to STA failing some reports
2366187 Tempus errors out while writing out SDF
2364603 write_timing_model (do_extract_model) SEGV
2364008 eco_opt_design -drv initial summary has a huge TNS number and WNS is NA
2363177 Errors during update_glitch
2357767 Using report_noise_format TCL var messes up create_spice_deck run simulation results
2355035 waveform_* properties giving "ERROR: (IMPESI-512): Encountering an internal error through get_property
2355026 DSTA-1007: Bad value (rise), expecting floating point number for "slack_min/max_edge" property
2355018 Align report_property output of collection return type property same as STA ({…}) rather than empty
2353731 ETM .lib empty
2353431 Tempus errors out in IR-STA run during update_timing
2352643 set_quiet_attacker leaving dot files in directory that need to be cleaned up
2352136 Allow report_noise -quiet_nets -txtfile abc.gz to gzip the file
2351384 Errors during glitch analysis
2347712 Errors with bus_attacker_accuracy_mode 3
2345401 Attacker in decouple thresh 0.04 run is missing in decouple thresh 0.00 run
2340630 report_clock_timing errors TCLCMD-999 and TCLCMD-998 but works fine after all_fanout is run before it
2340489 Delay increase for instance in session with SIV -pg_pin and single list library set
2337584 IMPESI-4216 errors out during update_timing after SIVs
2330305 Glitch report to show nworst for failures
2329606 SDF does not exhibit waveform attenuation as seen in Spice deck/Tempus MPW report
2326424 TA-523 error in C-MMMC
2324939 Discrepancy between waveform aware pulse width checks and rail swing analysis
2321299 Errors in post mask Tempus ECO
2320990 Tempus errors out during update_library_set after read_design
2319731 If useOrigIdxForSubsetWeight:true fixLCSubset:true are not default with LC, then user control is needed
2319569 Protect default change in bus attacker so it does not change results unexpectedly
2318070 Out of memory issue
2313446 report_noise -threshold instance being reflected properly in the glitch report
2313399 Bus attacker reporting of capacitance is low for amount of noise reported
2310728 Incorrect spatial derate applied on net in PBA bounding_box mode
2309701 Wrong PBA delay for PAD cell having bidi pin
2308995 Requesting enhancement for set_instance_library to support collection directly
2308365 set_si_mode -individual_glitch_simulation_mode 1 causes Cpl from PI not to combine with Prp
2305098 Request to merge bus groups together from block boundaries during top level run
2304397 LVF and original_pin construct not getting written out for min_pulse_width in ETM
2304384 Tempus exits without a message during create_glitch_boundary_model
2302359 Voltage mismatch between MSV and RT/AAE due to incorrect related ground net
2301793 Invalid value 'enum' specified with '-retime' for 'report_chain'
2299400 In Tempus GUI, when ECO is run using interactive ECO or timing debug, Tempus generates invalid ECO commands.
2289558 Disables sweep and initialize clock much before RIP
2289398 Need property to identify cells without LVF (not without variation)
2288560 Add a warning message during Spice trace generation when the Spice deck generated is not using a conditional arc
2287833 Add curly brackets around net name when report_noise -format is used
2280741 select_setup_endpoints in TSO causes later OPT steps (Hold Opt) misrepresents setup summary headers as selected
2274123 Enhance SLBBV flow to allow different voltage spec for clock and data
2271779 Apply boundary model constraints to specific blocks/instances
2268890 Backport set_delay_cal_mode -eng_fixLoadCapForRopSimulation true
2264247 Scope Analysis - SCOPE-2213 errors due to incorrect netlist at a corner case in BM generation
2260689 Allow phase reporting for bus attacker components when LC is enabled
2255774 Block port's case_value is not applied to the pin connected to port in context run
2253802 IMPESI-3423 should not be applied to multi-stage cells
2253693 Enhance set_driving_cell for voltage interpolation
2253147 Boundary model has waveform with 2 timestamps causing IMPESI-3072
2239599 IMPESI-3423 is printing on multi-stage cells and preventing ROP from being performed
2238138 VH run_path_simulation Spice deck grabs area from 1st result rather than worst glitch Spice result and shows NaN
2233041 Propagate set_mutex_condition automatically
2215569 Tempus errors out for missing output_ccb definition in the input library
2213428 Populate empty fields in single line glitch format with a “-“
2209298 Tempus errors out when loading dotlibs without double quote data
2181322 create_spice_deck -run_path_simulation should pick the worst ROP corresponding to the worst RIP
2167323 check_timing should have unexpandable_clocks for clock pairs whose period is not calculated
2121432 Clock skew enabled ECO run errors out
1923770 Need timing metrics for "double clocking"
1828245 Incremental glitch ECO
1556720 Ability to continue constraint reading even after errors
1522334 Enhance create_spice_deck -run_path_simulation to print 0.0 instead of dashes for the ~0 percentage values
1313027 DSTA report_noise command switches differ from STA
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Fixed CCRs in Voltus 21.10 RTM
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2451263 Voltus rail analysis fails after using skip_extraction due to incomplete net
2445461 Enhance the error message that appears when the number of nodes is over the limit
2442844 generate_esd_rlrp_report does not write JSON file, while extraction is done and ESD check has found paths
2438500 Voltus is not able to generate standard cell PGV models using Spectre SPICE files
2436630 Bogus warning messages for package
2436576 analyze_self_heat is picking glitch power for dtFEOL calculation
2434058 analyze_rail errors out during the reporting stage due to negative voltage rail (vdds = -0.6)
2432950 Voltus fails if Freq > 1 Ghz in validate_pg_library -frequency
2432042 Error in loading EffR domain results when one PG net has zero EffR output data
2430882 Error when using boundary voltage file
2430400 Change REFF reporting to include all user-requested nodes
2429137 Voltus errors out during the unified power flow
2429075 Failed to read RTL VCD
2428973 ESR values not reported with check_pg_library for memory PGV
2428463 Remove unnecessary warnings for missing decap filler cells in the distributed run
2428450 File length mismatches during standard cell PGV generation
2428290 VCE Flow - White space issue in the clock spec file and enhance the flow for error message impvcm-63
2425447 N16 Design: Error during power calculation when running place_opt_design
2424252 validate_pg_library command is creating set_power_pads on the switch net of a powergate cell
2424226 set_signal_em_analysis_mode option -net_freq_file to become public
2423418 Standard cell PGV should have trim feature to remove user-specified cells and create new PGV
2423253 Batch command to remove legend from GUI
2422715 validate_pg_library -enable_xp true does not convert to set_rail_analysis_mode -enable_xp true
2422046 Interpolation issue for CCSP dynamic_current
2421652 Hierarchical power map merge error
2421163 validate_pg_library is not working correctly
2420985 Incorrect current waveform captured while using FSDB for PGV generation
2419149 Power map generation failed
2418891 Power map generation failed
2418314 Standard cell PGV generates LEF-based tech PGV if SPICE netlist is missing, should error out
2418073 GUI: Simvision GUI terminates on second current loading from command line
2417840 Standard cell PGV gets created in the distributed run directory if only 1 cell is present in the distributed mode
2417248 Toggle rate differences between CPE and PM if set_default_switching_activity uses the ratio options
2415349 Missing GDS during PGV generation should flag warning in the log/report
2414585 Voltus selected the wrong switch edge for instance, mismatching with VCD
2414573 Handle index_output CCSP syntax
2414529 Incorrect TWF delay interpretation in power
2413808 Structural check failure for Voltus-Fi cells
2412322 GDS2DEF : Ports derived from label locations need to be enclosed within the corresponding metal layer width
2411933 add_reinforce_pg reports 0 tiles with IR violations though there are several instances with IR violations
2411761 Unconnected nets which are caused by "HARDSPACING" keyword in DEF
2411676 Enhancement to support load_side_file in voltus_power
2411598 ESR value is not reported correctly for memory PGV generation
2411535 Error during clockopt reporting stage
2411435 Incorrect auto-generated LEF layermap during PGV generation
2411420 Tool is not generating the correct voltus_gds_layer_map.txt file in the gds2def flow
2410956 Error during dynamic ERA in common UI
2410821 Improve IMPVAC-176 error to indicate extended SPEF must be used with read_spef -extended in the Signal EM flow
2410337 Signal EM reports fixWidth if em_threshold is less than 1
2408382 Voltus cannot generate a thermal model file when design is loaded via read_db/restoreDesign
2407988 validate_pg_library to support user-provided vsrc/ploc (XY Based)
2404318 ERA current region is not honored
2401852 REFF: Enhancement for reporting Reff on the user-specified nodes
2399703 GDS2DEF to report the shorted net and the mapped net information in the log file
2399384 Error in SPEF handling
2399376 XP: Voltus power error after completing power analysis successfully
2399214 LibGen footer cell error during Spectre simulation
2398936 Thermal enhancement for library-based leakage temperature in the scale table file
2365985 High runtime issue while characterizing GDHS cells for Ron
2365951 GDS2DEF output DEF is missing D6 shapes which are present in GDS
2365472 Voltus extractor errors out during rail analysis
2365293 check_pg_library to have the -cell_list option
2365183 Voltus GUI UPS flow
2364885 Processing signal activity takes more than 14 hours during report_power
2364852 Enhancement to consider inferred clock gates as normal gates during activity propagation
2363930 GDS2DEF to support writing DEF with 4000 db units
2361909 check_pg_library does not honor some of the checks in the rule file
2361845 check_pg_library -check_parameters is not working for Ron/Idsat/Ileak check for power gates
2361841 Enhancements for LEF consistency checks in check_pg_library
2361741 Need error checking for the distributed_setup file
2361174 Handle CPODE Leakage derate part of Voltus power analysis
2360709 Provide option to modify PWL units in the current region file
2360337 Signal EM separate report for average and peak results
2357768 Need area/peak comparison of input PG current FSDB vs PG current captured in memory PGV and dump a comparison report
2355683 DP/XP: Enhance scheduler and NTX to honor qrcTechFile
2355346 Current peak distance is increasing period after period
2355328 XP 3DIC should support layer-based via clustering
2353560 Signal EM RMS and peak .gif show larger percentage of "- nan -inf"
2353518 Activity is altered at clock step resulting in incorrect internal power for a macro
2353412 Map set_power_analysis_mode -enable_pte_flow to CUI
2352715 create_what_if_shape error
2352117 validate_pg_library errors out for memory PGV if LEF/lib used are bit-blasted
2352026 Rail analysis error
2349392 Voltus cannot generate the correct power map when the tile size is larger than 100x100
2349085 rHonorTwfPrecedenceDP causes switching scenario changes
2348393 VOLTUS_DP: Color mask shift inconsistent between DEF and LEF, and tool errors out
2348093 Missing DIEAREA information in DEF generated by create_what_if_shape
2348080 PLOC snapping issue on what-if shapes
2346868 Update TCL to run SpeedEM and PowerDC from Voltus
2346723 read_power_rail_results error when trying to load the power.db data
2344470 Voltus errors out during ERA
2343865 Fix a name in Voltus GUI
2343520 Tool hangs during the "Begin Preparing Data for Rail Analysis" stage
2342251 DGUI unable to use dbGet to get resistor drop and query_resistor does not have any filter capability
2342109 High runtime during IPF-based rail analysis
2340933 Trouble generating RAM PGV with Quantus SPICE
2339011 DP power needs an option to add power.inc only to the top-level job
2338236 No RLRP trace path found while querying any resistors over the GUI
2337705 Empty output directory while enabling distributed processing in PGV generation
2337605 Package error due to abnormal value
2337045 LibGen to ignore obstructions in LEF
2336735 Dynamic average current is not matching the static current when "enable_dynamic_scaling" is set to true
2335794 gds2def flow error
2335717 GUI behavior for the scale of layout in power plots
2335251 ChipPwr rWriteClockInstanceFileExcludeReg 1 to exclude memory macros
2334734 Need all enable pin (control pins) details in the switch cell PGV report
2333681 "-rv_length_benefit_disabled_layers" is not a legal option for command "verify_AC_limit"
2333648 Shorts are not reported in voltus_short.report
2332926 GDS2DEF utility is not working correctly with the streamout layermap file
2332348 Need user controllability for via insertion
2332007 Enhancement for EIV reporting/calculation for dynamic (VCD and Vless) flow
2331988 Enhancement for annotation reports in the dynamic vector-based flow
2331002 GUI result is not matching with text result of the rj plot
2330864 Frequency units to be changed to MHZ in the signal EM em ratio file
2330722 Multi-VCD activity annotation to consider worst activity with duty if activity is the same
2330434 Error in the Extraction stage
2330259 Missing files while rail analysis with NTX
2330084 Run with specify_lib command hangs while execution
2329990 Need to compress summary file while generating tech PGV to have runtime benefit
2329621 Ignore switching and internal power for cell with type "pad_cell = true " in Liberty
2328440 Physical cells being reported in the combinational cell category in IPF/Design Coverage Reporting
2328239 TWF stats information in the log and power.missing_data.twf files
2327820 Add DP and rail command option for extraction
2325700 Voltus extraction error
2325538 Need an option to toggle the MBFF output bits in both direction
2324837 tap_node_distance cannot be reported in the summary file
2323756 DP: scale_what_if_current causes the CID flow to be disabled
2323501 rj rendering issue over I/Ilimit value
2323146 Rail analysis adds voltage source on switched net of IO pad resulting in incorrect RLRP
2322194 Instance toggle rate plot is incorrect
2322106 RLRP is not tracing to the selected node/resistor segment
2322034 FSDB scope mapping fails when name ends with "/"
2321951 Error while running place_opt_design
2321216 Long runtimes for PGV generation
2320376 Error when running consecutive power analysis
2319829 Enhancement to change the instance number limitation in DGUI
2319824 Error when reading trigger condition for multiple memory in the same file
2319663 SPICE netlist parsing error
2319601 Enhancement for two-column mapping file to be case-insensitive for Dynamic VCD analysis
2318683 Rush current wake-up time is N/A
2318056 Legend option is missing from GUI
2315905 Provide an option to filter out non-violating signal EM wire violation segments from the report
2315704 Voltus SPA flow - dynamic package analysis neither creates probes nor runs simulation using Speed2000
2315550 Need Voltus-Fi models to take precedence over standard cell PGV
2315158 Need an option to place the current waveform at output toggle time for computational cells on data network
2315157 MBFF Q pin alignment issue in NAD0/1
2314466 GUI histogram and advance binning do not match
2314417 static_ir: Negative vddmx current, also seen in *.ptiavg file data as well
2314408 GUI in basic mode: bin filter is not working as expected
2313438 write_tcf -annotated after reading VCD file is not dumping annotations
2312979 Enhancement to add an option for ignoring the floating pins in rail analysis
2312472 read_db shows error while reading the power constraints
2312451 Multi-driver net analysis shows EM violations
2311844 Need automation for distributed power analysis flow, thereby having consolidated power reports
2311789 static_ir total power summary does not match the detailed power report for macro
2311527 SHE flow with report_power_in_parallel should wait for instance_power_file to be created
2310801 GUI issue while loading results for a net having special characters in its name
2310116 Voltus SPA flow generates IV files with NA for the package pin names
2309307 Tool errors out when executing the dump_unannotated_nets command
2308976 Difference in Signal EM values between 18.12 and 19.12
2308871 Signal EM GUI lacks result browser
2307773 Rail analysis reported cap not matching xPGV C2 cap value
2307444 Need an option to spread instances scheduled by input activity
2307234 Tool error with dynamic power optimization
2306786 Macro PGV generation error
2306472 Voltus errors out when a DDV has a PG pin trigger pin
2304564 XP to retain extraction debug logs
2303517 GDS-based PGV failing in the distributed mode
2303249 Need input scheduling fixes to be backported to the 1866 branch
2301857 PGV generation for some switch cells is failing
2301138 Signal EM - VAC fails in the simulation mode on the net with only AP layer due to annotation
2300391 MBFF mapping
2300253 Instance disconnects during the mergegrid stage
2298723 Power gate Idsat Ileak Ron are not reported with the -exclude_cell_list_file option
2298599 Extraction issue over a PG net
2298304 Power gate cell PGV report is incorrect
2297821 analyze_resistance error
2297221 XP Stylus: voltus_dist_power.summary does not include partition information
2296504 Undefined supply rail due to default voltage caused MVMF PGV to snap to wrong corner
2296339 Standard cell report generated for the master cell and the EEQ cell are different
2294296 Need an option to schedule new flops/macros every cycle instead of every two cycles
2294190 Standard cell PGV generation error during cap simulation
2293856 Self-heat parameters are not supported in Signal EM
2293798 Voltus does not report some wire segments in the signal EM report
2293600 Mapping issues for memory PGV generation with peak current
2293586 Issues with datasheet_delay and leakage current of macro's PGV generated by peak current
2293442 Combine power prints extra empty reports that are not generated in the original run
2293267 Give an option to combine reports without lighter version of power analysis
2293225 Demand current based die model to dump out current waveforms
2293213 Instance probing to support pin-based probing
2291953 IPF/Design Coverage Reporting enhancement when the IPF is read through the set_power command
2291933 PGEM to print the switched net/always-on net in the report with the unified power switch
2291809 PG pins are not reported for fillers/decap cells
2291405 Signal EM cdf_percentage is not set
2290229 Voltus errors out when EM cdf_percentage is not set
2289985 Issue with self-heat analysis
2289740 MIMCAP IR/EM views are not automatically used when accuracy is set to hd
2289661 VAC errors out during the analysis in the simulation mode
2288977 XP power-only flow command does not work in Stylus
2288918 Failed to run voltus_rail_smg
2288286 Need to extend max supported length for instance name to more than 4k
2288129 analyze_signal_resistance: dump layer name and pin xy location in the output report
2288122 analyze_resistance: dump layer name and pin xy location in the output report
2287802 State propagation files out of combine_distributed_power_reports are empty
2287012 Thermal flow input specification for signal EM
2286707 PGV generation is failing for the multiple technology LEF case
2286679 Command required for grouping switched nets if the names of the top and RDL nets are different
2286502 Voltus reports larger peak EM violation when running dynamic power EM analysis
2285308 Support for the layout scaling factor "setvar layout_scale scale_factor" in the XP flow
2285228 Switching scenario changes when rUseMacroToggleTimeFixInScheduling is enabled
2285186 XP to support pre-defined uniform density option
2284639 Power does not provide a proper stack trace after an error
2284580 Tool unable to trace the correct RLRP path for memory pins
2283544 Need to support the TWF constant net during dynamic vector-based analysis, but maintain VCD precedence over TWF
2282998 validate_pg_library does not honor the dynamic switch pattern
2282879 Enhancement to include modes in single PGV set
2282262 Switchinst report from vector-based analysis needs to print relative time instead of absolute time
2282081 Seeing high difference in IR numbers between 18.17 and 19.14
2281743 DP/XP: EM report bucketing should be fixed and not dependent on EM threshold
2281645 Remove some warnings related to the gate netlist view
2281280 SpectreOptions in thunder.inc is not adding Spectre parameters during coupling cap run
2281106 HDB GUI: DEF Pin should not be classified as "Cell Pin"
2280355 "Node Reff" value is "0" instead of "NA"
2279977 MBFF handling options are causing an unexpected change in the sequential coverage
2279233 Voltus errors out when processing netlist for power calculation in the distributed mode
2278967 setvar process_sub_conducting_layers false is not working
2278768 Error when reading the name mapping rule
2278546 Node probing – the map file is in the PGDB directory and not in the Report directory
2278182 Need the RLRP report to show the internal net name post the switch cell name
2278023 DGUI: Inconsistency in the display of the instance loading capacitance plot
2278020 DGUI: dd (Capacitance Density) plot shows NaN in the color range
2277919 Report instance toggling information in picoseconds (which is currently in ns) to distinguish the events
2277299 Change current construction from two peaks to a single peak
2277030 Combinational leakage power discrepancy between clock stage and the reload session
2276520 Miscorrelation in switching scenarios between two release versions
2276516 Spectre errors out in the distributed mode during memory PGV generation
2275064 Difference in the leakage power report for macros between two builds
2274804 "set_power -reset" causing ERROR and exits Voltus
2274318 Standard cell PGV is not generating cap values without the -filler_cells option in the distributed mode
2274289 Support multiple instance power files with the "set_power -ascii_power_file" command
2274018 combine_distributed_power_report does not create consolidated power.rpt in the output directory
2273803 Issue with parsing an instance name that is similar to the instance name of a DP power instance
2273272 Mixed-mode power analysis is overwriting activity of primary inputs mapped from RTL-VCD
2273271 Lower coverage with FSDB compared to VCD
2273014 RAM power miscorrelation between the DP and block-level runs
2272970 Roll-up file format changes in the Power EM flow
2272967 Roll-up file format changes in the Signal EM flow
2272938 report_power output report is showing NA
2272618 Very large current on the VSS rail in the static analysis flow
2272512 Error when report_power is run with the -no_wrap option
2271692 Need a new current generation method that does both peak preservation and charge preservation in the dynamic current waveform
2271554 Voltus errors out when the report_power_rail_results command is run
2271030 Non-switching cap scale factor does not cause any change in the capacitance report
2270180 Enhance the read_power_rail_results command to load hierarchical block results
2269921 Parsing of RTL VCD with auto-mapping enabled takes a long time
2269807 Voltus VCD parser error on [optimize out] syntax generated by Xcelium
2269365 Tool prints multiple different effective resistance values for the same node
2268912 DP: current is not reported for instances under 2 levels of power switches
2268867 switchinst and switchsrc files are not generated for two or more FSDB files
2268844 Extraction error in the full-chip run
2268121 Voltus should check for minimum one power and one ground net in the incomplete net flow
2268086 Voltus to print circuit profile of a net with all disconnected taps
2266496 Add voltage sources at the output pins of LDO
2266275 Add an option to provide voltage source location during PGV generation
2265476 Intermittent hang issue during extraction initialization
2265174 Dynamic validation for memory PGV does not work for multi-mode operation
2264504 Ignore unsupported options in the scan analysis flow by default
2264273 Power current differences seen with and without NAD
2262860 Enhancement to short LEF pins in a cell
2262742 Signal EM FIT reported as 0
2261903 Stylus support for the PGEM options
2261896 Stylus support for the Signal EM options
2261792 Voltus is calculating incorrect power for an instance when disable_leakage_scaling is set to true
2261345 Error while reading in the overlay DEF
2261286 DP_POWER: Instance connected to PI is not switching as expected and the switchsrc file has input pins
2261271 Need consolidated report for scan analysis
2261257 Voltus is misinterpreting an instance name when the name is similar to that of a DP power job
2259110 GUI/DGUI: Add a new button "plot" in the Short GUI form
2258538 MBFF support in Tempus PI
2258497 Signal EM: Top-level net with routing on the AP layer only is failing in the simulation mode
2258203 Stop the analysis flow when package simulation is diverging from the solution
2257787 Limit the maximum sequential activity to be 2x the global activity target
2257631 Tech-only PGV is not generated for OA
2256440 Need additional enhancements to the itaputil utility
2255346 SEM analysis errors out when reading qrcTechFile
2254237 Large difference in IR drop violations before and after restoreDesign
2254039 Lower hierarchy internal power net is missing from the voltus_pgrail.map and voltus_design.hierarchy.pgmap files when power analysis is run in the distributed mode
2253363 Difference in REFF value between tool created node-list pair versus user provided node-list pair
2253109 Enhancement to mark nodes from the REFF node list as label ports if loading vsrc from the ploc file
2252577 DP: The dominant frequency is 24MHz instead of 200MHz for a testcase
2252008 Enhance flop ranking reuse feature to allow top to bottom transfer of ranking data
2251948 Implementing PWL based Voltus source functionality in clock jitter analysis
2251071 GUI: Ability to load custom file without having to load state directory
2250349 DGUI: Remove empty layers from GUI
2249874 0 input scheduled even with 100% -input_activity settings
2249789 Lower-level power net is not getting the correct voltage because block instance prefix was not removed
2248999 Macro output pin scheduling problem: all the output pins only schedule rise, no fall and no alternation
2248194 Transition density calculation is incorrect when handle_glitch is set to true
2248026 Signal EM violation on customer cell
2246184 Spectre errors out in the distributed mode for standard cell PGV generation
2245025 Calling "report_power" without "set_power_output_dir" causes subsequent "reinforce_pg" to fail
2244445 LibGen to use the technology GDS layer map file for creation of the PGV models
2244410 XP: Some of the tran_<net>.X.ptiavg files still remain in the waveform directory
2243912 Improve "NoScheduled" flag in voltus_power.stateprop.noswitchinst
2242986 Instance EFFR report does not honor the report pin layer
2242149 probe_waveform_list prints incorrect warning in the log
2242055 Extraction stop layer is promoting taps from the lower layers
2241786 Voltus errors out when running the state propagation flow with the debug option
2241513 dynamic_switch_pattern { - - } is not honored with -no_propagation
2241240 RLRP and EFFR report number of nodes to honor report layer setting and add another column for reporting layer
2240971 set_switching_activity -pin_type input should not set activity on clock pins
2239802 Time taken to run set_switching_activity -inst is more when it is run after set_switching_activity -pin
2238080 Enhancement to handle output pins of memories with switch pattern
2237981 PGV loading time of 45 minutes per power partition in XP with approx 6000 PGVs including DDVs
2237378 report_vector_profile ignores IO power
2236698 Include pin layer name for the shorted clamp report
2234495 Error when loading the rail database and effective resistance report
2234370 Include the ESD pin tag information in .report
2233469 Extraction to support back side metals
2233416 PGV to support back side metals
2230067 GDS2DEF utility to use the technology GDS layer map file (used by Innovus)
2228428 Intermittent errors during Voltus package analysis
2227507 Support for a user-specified voltage for waveform shaping in rail
2227503 Support for a user-specified voltage for library binding in power
2225885 Need support for pin-based load cap assignment with pin-based current generation
2225301 set_power_pads -short_pin_nodes true is not working as expected
2225294 instance_ir report prints incorrect worst node location
2222837 Check for Tempus behavior of "set_power_analysis_mode -enable_view_pruning true"
2219943 Voltus to promote only pin shapes for the decap and filler cells
2213004 Inconsistency seen in the reason for not switching at different scenarios for a particular condition
2210967 B2C : GUI display for REFF report with shorted clamps
2210005 /tmp fills up even when TMPDIR or -temp_directory_name points to a different location
2209216 Support different dynamic power mode per DP block
2202210 Voltus to generate user-specified region-based die model
2199857 Histogram of Jrms report is missing
2199638 Current value is not distributed to the specified block in the domain-based analysis
2199230 Enhance the read_activity_file -format option to handle either upper or lower case in both legacy and Stylus
2196829 Enhancement for supporting mixed VCD RTL and Gate-level with delay annotation at the same block
2183281 FSDB with chopped smaller window gives higher current in the first cycle
2181553 GUI enhancement: ESD to bump results display
2181163 Change reference point of the shorted bump-to-clamp check
2173934 Enable RLRP analysis (layer-based resistance reporting) in the ESD B2C flow
2171910 gds2def flow needs to include mask information in the 7/5nm process
2164839 Negative bias voltage is not reported in the static power output report
2161384 Scale what-if flow to work without set_top_module
2149118 MBFF pin scheduling based on flop fanout count of individual pins
2144750 Issues with DEF reading related to intermediate hierarchy during power analysis
2127418 DGUI: Instance toggle rate plots ar eincorrect
2125968 Virtus report_power in PARADIME client will need to have absolute path for TWF file
2121285 Rail analysis report if master or slave swaps physical memory
2097868 [Power DP/Power Calculation] Converted tbin loading issue for a particular design hierarchy
2074490 Guarantee full coverage for MBFF and macro output pin schedule
2048333 Enhance -report_instance_switching_info to compress voltus_power.stateprop.switchinst on the fly
2045350 P/G extraction should be not re-run if report_resistance is run immediately after report_rail
2042766 Voltus enhancement for dynamic switching scenario file
2027892 Need to include current regions on switched rail
2022153 map_activity_file should support gzipped files
1993851 Accurate supply current modeling for resistive shielding
1989451 Rail analysis integrated in ccopt_design fails to affect refinePlace
1929967 Duplication of macro power during the ERA power calculation
1924380 Need ERA rail to assign macro current only for the pins which are connected to the nets analyzed in rail
1893022 read_power_rail_results -file_name results incorrect when -filter_min == -range_min
1830163 ERA is not honoring placement blockages
May 14, 2021
Fixed CCRs in Tempus 21.10 RTM
=================================================
2452798 Incorrect minimum rise delay reported
2447608 IMPESI-3194 errors in PGV flow
2443803 Stylus Tempus DSTA uses Legacy UI command when running in CUI mode "-distributed -stylus -wait 20 -cpus 2 -nowin"
2442861 High run time with Tempus leakage ECO with low fix rate and .summary file not getting dumped
2440312 apply_boundary_model_constraints does not accept a "-" in the bus bundle name
2434416 set_cdb_binding is not logged in the logv/cmd file
2434398 Larger than expected run time increase of bus over nobus run
2429552 Paths go unconstrained inconsistently in C-MMMC
2429475 Tempus eco_opt_design -power degrades setup time
2421061 set_disable_timing not working on library cell arc and not throwing any error
2417838 Give info message when reading in constraints from boundary model
2413011 Boundary model should not save annotated glitch for TAIgnored nets
2408473 Attribute mapping load_pins to leaf_load of net type not working in DSTA compared to STA failing some reports
2366187 Tempus errors out while writing out SDF
2364603 write_timing_model (do_extract_model) SEGV
2364008 eco_opt_design -drv initial summary has a huge TNS number and WNS is NA
2363177 Errors during update_glitch
2357767 Using report_noise_format TCL var messes up create_spice_deck run simulation results
2355035 waveform_* properties giving "ERROR: (IMPESI-512): Encountering an internal error through get_property
2355026 DSTA-1007: Bad value (rise), expecting floating point number for "slack_min/max_edge" property
2355018 Align report_property output of collection return type property same as STA ({…}) rather than empty
2353731 ETM .lib empty
2353431 Tempus errors out in IR-STA run during update_timing
2352643 set_quiet_attacker leaving dot files in directory that need to be cleaned up
2352136 Allow report_noise -quiet_nets -txtfile abc.gz to gzip the file
2351384 Errors during glitch analysis
2347712 Errors with bus_attacker_accuracy_mode 3
2345401 Attacker in decouple thresh 0.04 run is missing in decouple thresh 0.00 run
2340630 report_clock_timing errors TCLCMD-999 and TCLCMD-998 but works fine after all_fanout is run before it
2340489 Delay increase for instance in session with SIV -pg_pin and single list library set
2337584 IMPESI-4216 errors out during update_timing after SIVs
2330305 Glitch report to show nworst for failures
2329606 SDF does not exhibit waveform attenuation as seen in Spice deck/Tempus MPW report
2326424 TA-523 error in C-MMMC
2324939 Discrepancy between waveform aware pulse width checks and rail swing analysis
2321299 Errors in post mask Tempus ECO
2320990 Tempus errors out during update_library_set after read_design
2319731 If useOrigIdxForSubsetWeight:true fixLCSubset:true are not default with LC, then user control is needed
2319569 Protect default change in bus attacker so it does not change results unexpectedly
2318070 Out of memory issue
2313446 report_noise -threshold instance being reflected properly in the glitch report
2313399 Bus attacker reporting of capacitance is low for amount of noise reported
2310728 Incorrect spatial derate applied on net in PBA bounding_box mode
2309701 Wrong PBA delay for PAD cell having bidi pin
2308995 Requesting enhancement for set_instance_library to support collection directly
2308365 set_si_mode -individual_glitch_simulation_mode 1 causes Cpl from PI not to combine with Prp
2305098 Request to merge bus groups together from block boundaries during top level run
2304397 LVF and original_pin construct not getting written out for min_pulse_width in ETM
2304384 Tempus exits without a message during create_glitch_boundary_model
2302359 Voltage mismatch between MSV and RT/AAE due to incorrect related ground net
2301793 Invalid value 'enum' specified with '-retime' for 'report_chain'
2299400 In Tempus GUI, when ECO is run using interactive ECO or timing debug, Tempus generates invalid ECO commands.
2289558 Disables sweep and initialize clock much before RIP
2289398 Need property to identify cells without LVF (not without variation)
2288560 Add a warning message during Spice trace generation when the Spice deck generated is not using a conditional arc
2287833 Add curly brackets around net name when report_noise -format is used
2280741 select_setup_endpoints in TSO causes later OPT steps (Hold Opt) misrepresents setup summary headers as selected
2274123 Enhance SLBBV flow to allow different voltage spec for clock and data
2271779 Apply boundary model constraints to specific blocks/instances
2268890 Backport set_delay_cal_mode -eng_fixLoadCapForRopSimulation true
2264247 Scope Analysis - SCOPE-2213 errors due to incorrect netlist at a corner case in BM generation
2260689 Allow phase reporting for bus attacker components when LC is enabled
2255774 Block port's case_value is not applied to the pin connected to port in context run
2253802 IMPESI-3423 should not be applied to multi-stage cells
2253693 Enhance set_driving_cell for voltage interpolation
2253147 Boundary model has waveform with 2 timestamps causing IMPESI-3072
2239599 IMPESI-3423 is printing on multi-stage cells and preventing ROP from being performed
2238138 VH run_path_simulation Spice deck grabs area from 1st result rather than worst glitch Spice result and shows NaN
2233041 Propagate set_mutex_condition automatically
2215569 Tempus errors out for missing output_ccb definition in the input library
2213428 Populate empty fields in single line glitch format with a “-“
2209298 Tempus errors out when loading dotlibs without double quote data
2181322 create_spice_deck -run_path_simulation should pick the worst ROP corresponding to the worst RIP
2167323 check_timing should have unexpandable_clocks for clock pairs whose period is not calculated
2121432 Clock skew enabled ECO run errors out
1923770 Need timing metrics for "double clocking"
1828245 Incremental glitch ECO
1556720 Ability to continue constraint reading even after errors
1522334 Enhance create_spice_deck -run_path_simulation to print 0.0 instead of dashes for the ~0 percentage values
1313027 DSTA report_noise command switches differ from STA
=================================================
Fixed CCRs in Voltus 21.10 RTM
=================================================
2451263 Voltus rail analysis fails after using skip_extraction due to incomplete net
2445461 Enhance the error message that appears when the number of nodes is over the limit
2442844 generate_esd_rlrp_report does not write JSON file, while extraction is done and ESD check has found paths
2438500 Voltus is not able to generate standard cell PGV models using Spectre SPICE files
2436630 Bogus warning messages for package
2436576 analyze_self_heat is picking glitch power for dtFEOL calculation
2434058 analyze_rail errors out during the reporting stage due to negative voltage rail (vdds = -0.6)
2432950 Voltus fails if Freq > 1 Ghz in validate_pg_library -frequency
2432042 Error in loading EffR domain results when one PG net has zero EffR output data
2430882 Error when using boundary voltage file
2430400 Change REFF reporting to include all user-requested nodes
2429137 Voltus errors out during the unified power flow
2429075 Failed to read RTL VCD
2428973 ESR values not reported with check_pg_library for memory PGV
2428463 Remove unnecessary warnings for missing decap filler cells in the distributed run
2428450 File length mismatches during standard cell PGV generation
2428290 VCE Flow - White space issue in the clock spec file and enhance the flow for error message impvcm-63
2425447 N16 Design: Error during power calculation when running place_opt_design
2424252 validate_pg_library command is creating set_power_pads on the switch net of a powergate cell
2424226 set_signal_em_analysis_mode option -net_freq_file to become public
2423418 Standard cell PGV should have trim feature to remove user-specified cells and create new PGV
2423253 Batch command to remove legend from GUI
2422715 validate_pg_library -enable_xp true does not convert to set_rail_analysis_mode -enable_xp true
2422046 Interpolation issue for CCSP dynamic_current
2421652 Hierarchical power map merge error
2421163 validate_pg_library is not working correctly
2420985 Incorrect current waveform captured while using FSDB for PGV generation
2419149 Power map generation failed
2418891 Power map generation failed
2418314 Standard cell PGV generates LEF-based tech PGV if SPICE netlist is missing, should error out
2418073 GUI: Simvision GUI terminates on second current loading from command line
2417840 Standard cell PGV gets created in the distributed run directory if only 1 cell is present in the distributed mode
2417248 Toggle rate differences between CPE and PM if set_default_switching_activity uses the ratio options
2415349 Missing GDS during PGV generation should flag warning in the log/report
2414585 Voltus selected the wrong switch edge for instance, mismatching with VCD
2414573 Handle index_output CCSP syntax
2414529 Incorrect TWF delay interpretation in power
2413808 Structural check failure for Voltus-Fi cells
2412322 GDS2DEF : Ports derived from label locations need to be enclosed within the corresponding metal layer width
2411933 add_reinforce_pg reports 0 tiles with IR violations though there are several instances with IR violations
2411761 Unconnected nets which are caused by "HARDSPACING" keyword in DEF
2411676 Enhancement to support load_side_file in voltus_power
2411598 ESR value is not reported correctly for memory PGV generation
2411535 Error during clockopt reporting stage
2411435 Incorrect auto-generated LEF layermap during PGV generation
2411420 Tool is not generating the correct voltus_gds_layer_map.txt file in the gds2def flow
2410956 Error during dynamic ERA in common UI
2410821 Improve IMPVAC-176 error to indicate extended SPEF must be used with read_spef -extended in the Signal EM flow
2410337 Signal EM reports fixWidth if em_threshold is less than 1
2408382 Voltus cannot generate a thermal model file when design is loaded via read_db/restoreDesign
2407988 validate_pg_library to support user-provided vsrc/ploc (XY Based)
2404318 ERA current region is not honored
2401852 REFF: Enhancement for reporting Reff on the user-specified nodes
2399703 GDS2DEF to report the shorted net and the mapped net information in the log file
2399384 Error in SPEF handling
2399376 XP: Voltus power error after completing power analysis successfully
2399214 LibGen footer cell error during Spectre simulation
2398936 Thermal enhancement for library-based leakage temperature in the scale table file
2365985 High runtime issue while characterizing GDHS cells for Ron
2365951 GDS2DEF output DEF is missing D6 shapes which are present in GDS
2365472 Voltus extractor errors out during rail analysis
2365293 check_pg_library to have the -cell_list option
2365183 Voltus GUI UPS flow
2364885 Processing signal activity takes more than 14 hours during report_power
2364852 Enhancement to consider inferred clock gates as normal gates during activity propagation
2363930 GDS2DEF to support writing DEF with 4000 db units
2361909 check_pg_library does not honor some of the checks in the rule file
2361845 check_pg_library -check_parameters is not working for Ron/Idsat/Ileak check for power gates
2361841 Enhancements for LEF consistency checks in check_pg_library
2361741 Need error checking for the distributed_setup file
2361174 Handle CPODE Leakage derate part of Voltus power analysis
2360709 Provide option to modify PWL units in the current region file
2360337 Signal EM separate report for average and peak results
2357768 Need area/peak comparison of input PG current FSDB vs PG current captured in memory PGV and dump a comparison report
2355683 DP/XP: Enhance scheduler and NTX to honor qrcTechFile
2355346 Current peak distance is increasing period after period
2355328 XP 3DIC should support layer-based via clustering
2353560 Signal EM RMS and peak .gif show larger percentage of "- nan -inf"
2353518 Activity is altered at clock step resulting in incorrect internal power for a macro
2353412 Map set_power_analysis_mode -enable_pte_flow to CUI
2352715 create_what_if_shape error
2352117 validate_pg_library errors out for memory PGV if LEF/lib used are bit-blasted
2352026 Rail analysis error
2349392 Voltus cannot generate the correct power map when the tile size is larger than 100x100
2349085 rHonorTwfPrecedenceDP causes switching scenario changes
2348393 VOLTUS_DP: Color mask shift inconsistent between DEF and LEF, and tool errors out
2348093 Missing DIEAREA information in DEF generated by create_what_if_shape
2348080 PLOC snapping issue on what-if shapes
2346868 Update TCL to run SpeedEM and PowerDC from Voltus
2346723 read_power_rail_results error when trying to load the power.db data
2344470 Voltus errors out during ERA
2343865 Fix a name in Voltus GUI
2343520 Tool hangs during the "Begin Preparing Data for Rail Analysis" stage
2342251 DGUI unable to use dbGet to get resistor drop and query_resistor does not have any filter capability
2342109 High runtime during IPF-based rail analysis
2340933 Trouble generating RAM PGV with Quantus SPICE
2339011 DP power needs an option to add power.inc only to the top-level job
2338236 No RLRP trace path found while querying any resistors over the GUI
2337705 Empty output directory while enabling distributed processing in PGV generation
2337605 Package error due to abnormal value
2337045 LibGen to ignore obstructions in LEF
2336735 Dynamic average current is not matching the static current when "enable_dynamic_scaling" is set to true
2335794 gds2def flow error
2335717 GUI behavior for the scale of layout in power plots
2335251 ChipPwr rWriteClockInstanceFileExcludeReg 1 to exclude memory macros
2334734 Need all enable pin (control pins) details in the switch cell PGV report
2333681 "-rv_length_benefit_disabled_layers" is not a legal option for command "verify_AC_limit"
2333648 Shorts are not reported in voltus_short.report
2332926 GDS2DEF utility is not working correctly with the streamout layermap file
2332348 Need user controllability for via insertion
2332007 Enhancement for EIV reporting/calculation for dynamic (VCD and Vless) flow
2331988 Enhancement for annotation reports in the dynamic vector-based flow
2331002 GUI result is not matching with text result of the rj plot
2330864 Frequency units to be changed to MHZ in the signal EM em ratio file
2330722 Multi-VCD activity annotation to consider worst activity with duty if activity is the same
2330434 Error in the Extraction stage
2330259 Missing files while rail analysis with NTX
2330084 Run with specify_lib command hangs while execution
2329990 Need to compress summary file while generating tech PGV to have runtime benefit
2329621 Ignore switching and internal power for cell with type "pad_cell = true " in Liberty
2328440 Physical cells being reported in the combinational cell category in IPF/Design Coverage Reporting
2328239 TWF stats information in the log and power.missing_data.twf files
2327820 Add DP and rail command option for extraction
2325700 Voltus extraction error
2325538 Need an option to toggle the MBFF output bits in both direction
2324837 tap_node_distance cannot be reported in the summary file
2323756 DP: scale_what_if_current causes the CID flow to be disabled
2323501 rj rendering issue over I/Ilimit value
2323146 Rail analysis adds voltage source on switched net of IO pad resulting in incorrect RLRP
2322194 Instance toggle rate plot is incorrect
2322106 RLRP is not tracing to the selected node/resistor segment
2322034 FSDB scope mapping fails when name ends with "/"
2321951 Error while running place_opt_design
2321216 Long runtimes for PGV generation
2320376 Error when running consecutive power analysis
2319829 Enhancement to change the instance number limitation in DGUI
2319824 Error when reading trigger condition for multiple memory in the same file
2319663 SPICE netlist parsing error
2319601 Enhancement for two-column mapping file to be case-insensitive for Dynamic VCD analysis
2318683 Rush current wake-up time is N/A
2318056 Legend option is missing from GUI
2315905 Provide an option to filter out non-violating signal EM wire violation segments from the report
2315704 Voltus SPA flow - dynamic package analysis neither creates probes nor runs simulation using Speed2000
2315550 Need Voltus-Fi models to take precedence over standard cell PGV
2315158 Need an option to place the current waveform at output toggle time for computational cells on data network
2315157 MBFF Q pin alignment issue in NAD0/1
2314466 GUI histogram and advance binning do not match
2314417 static_ir: Negative vddmx current, also seen in *.ptiavg file data as well
2314408 GUI in basic mode: bin filter is not working as expected
2313438 write_tcf -annotated after reading VCD file is not dumping annotations
2312979 Enhancement to add an option for ignoring the floating pins in rail analysis
2312472 read_db shows error while reading the power constraints
2312451 Multi-driver net analysis shows EM violations
2311844 Need automation for distributed power analysis flow, thereby having consolidated power reports
2311789 static_ir total power summary does not match the detailed power report for macro
2311527 SHE flow with report_power_in_parallel should wait for instance_power_file to be created
2310801 GUI issue while loading results for a net having special characters in its name
2310116 Voltus SPA flow generates IV files with NA for the package pin names
2309307 Tool errors out when executing the dump_unannotated_nets command
2308976 Difference in Signal EM values between 18.12 and 19.12
2308871 Signal EM GUI lacks result browser
2307773 Rail analysis reported cap not matching xPGV C2 cap value
2307444 Need an option to spread instances scheduled by input activity
2307234 Tool error with dynamic power optimization
2306786 Macro PGV generation error
2306472 Voltus errors out when a DDV has a PG pin trigger pin
2304564 XP to retain extraction debug logs
2303517 GDS-based PGV failing in the distributed mode
2303249 Need input scheduling fixes to be backported to the 1866 branch
2301857 PGV generation for some switch cells is failing
2301138 Signal EM - VAC fails in the simulation mode on the net with only AP layer due to annotation
2300391 MBFF mapping
2300253 Instance disconnects during the mergegrid stage
2298723 Power gate Idsat Ileak Ron are not reported with the -exclude_cell_list_file option
2298599 Extraction issue over a PG net
2298304 Power gate cell PGV report is incorrect
2297821 analyze_resistance error
2297221 XP Stylus: voltus_dist_power.summary does not include partition information
2296504 Undefined supply rail due to default voltage caused MVMF PGV to snap to wrong corner
2296339 Standard cell report generated for the master cell and the EEQ cell are different
2294296 Need an option to schedule new flops/macros every cycle instead of every two cycles
2294190 Standard cell PGV generation error during cap simulation
2293856 Self-heat parameters are not supported in Signal EM
2293798 Voltus does not report some wire segments in the signal EM report
2293600 Mapping issues for memory PGV generation with peak current
2293586 Issues with datasheet_delay and leakage current of macro's PGV generated by peak current
2293442 Combine power prints extra empty reports that are not generated in the original run
2293267 Give an option to combine reports without lighter version of power analysis
2293225 Demand current based die model to dump out current waveforms
2293213 Instance probing to support pin-based probing
2291953 IPF/Design Coverage Reporting enhancement when the IPF is read through the set_power command
2291933 PGEM to print the switched net/always-on net in the report with the unified power switch
2291809 PG pins are not reported for fillers/decap cells
2291405 Signal EM cdf_percentage is not set
2290229 Voltus errors out when EM cdf_percentage is not set
2289985 Issue with self-heat analysis
2289740 MIMCAP IR/EM views are not automatically used when accuracy is set to hd
2289661 VAC errors out during the analysis in the simulation mode
2288977 XP power-only flow command does not work in Stylus
2288918 Failed to run voltus_rail_smg
2288286 Need to extend max supported length for instance name to more than 4k
2288129 analyze_signal_resistance: dump layer name and pin xy location in the output report
2288122 analyze_resistance: dump layer name and pin xy location in the output report
2287802 State propagation files out of combine_distributed_power_reports are empty
2287012 Thermal flow input specification for signal EM
2286707 PGV generation is failing for the multiple technology LEF case
2286679 Command required for grouping switched nets if the names of the top and RDL nets are different
2286502 Voltus reports larger peak EM violation when running dynamic power EM analysis
2285308 Support for the layout scaling factor "setvar layout_scale scale_factor" in the XP flow
2285228 Switching scenario changes when rUseMacroToggleTimeFixInScheduling is enabled
2285186 XP to support pre-defined uniform density option
2284639 Power does not provide a proper stack trace after an error
2284580 Tool unable to trace the correct RLRP path for memory pins
2283544 Need to support the TWF constant net during dynamic vector-based analysis, but maintain VCD precedence over TWF
2282998 validate_pg_library does not honor the dynamic switch pattern
2282879 Enhancement to include modes in single PGV set
2282262 Switchinst report from vector-based analysis needs to print relative time instead of absolute time
2282081 Seeing high difference in IR numbers between 18.17 and 19.14
2281743 DP/XP: EM report bucketing should be fixed and not dependent on EM threshold
2281645 Remove some warnings related to the gate netlist view
2281280 SpectreOptions in thunder.inc is not adding Spectre parameters during coupling cap run
2281106 HDB GUI: DEF Pin should not be classified as "Cell Pin"
2280355 "Node Reff" value is "0" instead of "NA"
2279977 MBFF handling options are causing an unexpected change in the sequential coverage
2279233 Voltus errors out when processing netlist for power calculation in the distributed mode
2278967 setvar process_sub_conducting_layers false is not working
2278768 Error when reading the name mapping rule
2278546 Node probing – the map file is in the PGDB directory and not in the Report directory
2278182 Need the RLRP report to show the internal net name post the switch cell name
2278023 DGUI: Inconsistency in the display of the instance loading capacitance plot
2278020 DGUI: dd (Capacitance Density) plot shows NaN in the color range
2277919 Report instance toggling information in picoseconds (which is currently in ns) to distinguish the events
2277299 Change current construction from two peaks to a single peak
2277030 Combinational leakage power discrepancy between clock stage and the reload session
2276520 Miscorrelation in switching scenarios between two release versions
2276516 Spectre errors out in the distributed mode during memory PGV generation
2275064 Difference in the leakage power report for macros between two builds
2274804 "set_power -reset" causing ERROR and exits Voltus
2274318 Standard cell PGV is not generating cap values without the -filler_cells option in the distributed mode
2274289 Support multiple instance power files with the "set_power -ascii_power_file" command
2274018 combine_distributed_power_report does not create consolidated power.rpt in the output directory
2273803 Issue with parsing an instance name that is similar to the instance name of a DP power instance
2273272 Mixed-mode power analysis is overwriting activity of primary inputs mapped from RTL-VCD
2273271 Lower coverage with FSDB compared to VCD
2273014 RAM power miscorrelation between the DP and block-level runs
2272970 Roll-up file format changes in the Power EM flow
2272967 Roll-up file format changes in the Signal EM flow
2272938 report_power output report is showing NA
2272618 Very large current on the VSS rail in the static analysis flow
2272512 Error when report_power is run with the -no_wrap option
2271692 Need a new current generation method that does both peak preservation and charge preservation in the dynamic current waveform
2271554 Voltus errors out when the report_power_rail_results command is run
2271030 Non-switching cap scale factor does not cause any change in the capacitance report
2270180 Enhance the read_power_rail_results command to load hierarchical block results
2269921 Parsing of RTL VCD with auto-mapping enabled takes a long time
2269807 Voltus VCD parser error on [optimize out] syntax generated by Xcelium
2269365 Tool prints multiple different effective resistance values for the same node
2268912 DP: current is not reported for instances under 2 levels of power switches
2268867 switchinst and switchsrc files are not generated for two or more FSDB files
2268844 Extraction error in the full-chip run
2268121 Voltus should check for minimum one power and one ground net in the incomplete net flow
2268086 Voltus to print circuit profile of a net with all disconnected taps
2266496 Add voltage sources at the output pins of LDO
2266275 Add an option to provide voltage source location during PGV generation
2265476 Intermittent hang issue during extraction initialization
2265174 Dynamic validation for memory PGV does not work for multi-mode operation
2264504 Ignore unsupported options in the scan analysis flow by default
2264273 Power current differences seen with and without NAD
2262860 Enhancement to short LEF pins in a cell
2262742 Signal EM FIT reported as 0
2261903 Stylus support for the PGEM options
2261896 Stylus support for the Signal EM options
2261792 Voltus is calculating incorrect power for an instance when disable_leakage_scaling is set to true
2261345 Error while reading in the overlay DEF
2261286 DP_POWER: Instance connected to PI is not switching as expected and the switchsrc file has input pins
2261271 Need consolidated report for scan analysis
2261257 Voltus is misinterpreting an instance name when the name is similar to that of a DP power job
2259110 GUI/DGUI: Add a new button "plot" in the Short GUI form
2258538 MBFF support in Tempus PI
2258497 Signal EM: Top-level net with routing on the AP layer only is failing in the simulation mode
2258203 Stop the analysis flow when package simulation is diverging from the solution
2257787 Limit the maximum sequential activity to be 2x the global activity target
2257631 Tech-only PGV is not generated for OA
2256440 Need additional enhancements to the itaputil utility
2255346 SEM analysis errors out when reading qrcTechFile
2254237 Large difference in IR drop violations before and after restoreDesign
2254039 Lower hierarchy internal power net is missing from the voltus_pgrail.map and voltus_design.hierarchy.pgmap files when power analysis is run in the distributed mode
2253363 Difference in REFF value between tool created node-list pair versus user provided node-list pair
2253109 Enhancement to mark nodes from the REFF node list as label ports if loading vsrc from the ploc file
2252577 DP: The dominant frequency is 24MHz instead of 200MHz for a testcase
2252008 Enhance flop ranking reuse feature to allow top to bottom transfer of ranking data
2251948 Implementing PWL based Voltus source functionality in clock jitter analysis
2251071 GUI: Ability to load custom file without having to load state directory
2250349 DGUI: Remove empty layers from GUI
2249874 0 input scheduled even with 100% -input_activity settings
2249789 Lower-level power net is not getting the correct voltage because block instance prefix was not removed
2248999 Macro output pin scheduling problem: all the output pins only schedule rise, no fall and no alternation
2248194 Transition density calculation is incorrect when handle_glitch is set to true
2248026 Signal EM violation on customer cell
2246184 Spectre errors out in the distributed mode for standard cell PGV generation
2245025 Calling "report_power" without "set_power_output_dir" causes subsequent "reinforce_pg" to fail
2244445 LibGen to use the technology GDS layer map file for creation of the PGV models
2244410 XP: Some of the tran_<net>.X.ptiavg files still remain in the waveform directory
2243912 Improve "NoScheduled" flag in voltus_power.stateprop.noswitchinst
2242986 Instance EFFR report does not honor the report pin layer
2242149 probe_waveform_list prints incorrect warning in the log
2242055 Extraction stop layer is promoting taps from the lower layers
2241786 Voltus errors out when running the state propagation flow with the debug option
2241513 dynamic_switch_pattern { - - } is not honored with -no_propagation
2241240 RLRP and EFFR report number of nodes to honor report layer setting and add another column for reporting layer
2240971 set_switching_activity -pin_type input should not set activity on clock pins
2239802 Time taken to run set_switching_activity -inst is more when it is run after set_switching_activity -pin
2238080 Enhancement to handle output pins of memories with switch pattern
2237981 PGV loading time of 45 minutes per power partition in XP with approx 6000 PGVs including DDVs
2237378 report_vector_profile ignores IO power
2236698 Include pin layer name for the shorted clamp report
2234495 Error when loading the rail database and effective resistance report
2234370 Include the ESD pin tag information in .report
2233469 Extraction to support back side metals
2233416 PGV to support back side metals
2230067 GDS2DEF utility to use the technology GDS layer map file (used by Innovus)
2228428 Intermittent errors during Voltus package analysis
2227507 Support for a user-specified voltage for waveform shaping in rail
2227503 Support for a user-specified voltage for library binding in power
2225885 Need support for pin-based load cap assignment with pin-based current generation
2225301 set_power_pads -short_pin_nodes true is not working as expected
2225294 instance_ir report prints incorrect worst node location
2222837 Check for Tempus behavior of "set_power_analysis_mode -enable_view_pruning true"
2219943 Voltus to promote only pin shapes for the decap and filler cells
2213004 Inconsistency seen in the reason for not switching at different scenarios for a particular condition
2210967 B2C : GUI display for REFF report with shorted clamps
2210005 /tmp fills up even when TMPDIR or -temp_directory_name points to a different location
2209216 Support different dynamic power mode per DP block
2202210 Voltus to generate user-specified region-based die model
2199857 Histogram of Jrms report is missing
2199638 Current value is not distributed to the specified block in the domain-based analysis
2199230 Enhance the read_activity_file -format option to handle either upper or lower case in both legacy and Stylus
2196829 Enhancement for supporting mixed VCD RTL and Gate-level with delay annotation at the same block
2183281 FSDB with chopped smaller window gives higher current in the first cycle
2181553 GUI enhancement: ESD to bump results display
2181163 Change reference point of the shorted bump-to-clamp check
2173934 Enable RLRP analysis (layer-based resistance reporting) in the ESD B2C flow
2171910 gds2def flow needs to include mask information in the 7/5nm process
2164839 Negative bias voltage is not reported in the static power output report
2161384 Scale what-if flow to work without set_top_module
2149118 MBFF pin scheduling based on flop fanout count of individual pins
2144750 Issues with DEF reading related to intermediate hierarchy during power analysis
2127418 DGUI: Instance toggle rate plots ar eincorrect
2125968 Virtus report_power in PARADIME client will need to have absolute path for TWF file
2121285 Rail analysis report if master or slave swaps physical memory
2097868 [Power DP/Power Calculation] Converted tbin loading issue for a particular design hierarchy
2074490 Guarantee full coverage for MBFF and macro output pin schedule
2048333 Enhance -report_instance_switching_info to compress voltus_power.stateprop.switchinst on the fly
2045350 P/G extraction should be not re-run if report_resistance is run immediately after report_rail
2042766 Voltus enhancement for dynamic switching scenario file
2027892 Need to include current regions on switched rail
2022153 map_activity_file should support gzipped files
1993851 Accurate supply current modeling for resistive shielding
1989451 Rail analysis integrated in ccopt_design fails to affect refinePlace
1929967 Duplication of macro power during the ERA power calculation
1924380 Need ERA rail to assign macro current only for the pins which are connected to the nets analyzed in rail
1893022 read_power_rail_results -file_name results incorrect when -filter_min == -range_min
1830163 ERA is not honoring placement blockages
May 14, 2021
Silicon signoff and verification (SSV) encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout. These steps report errors that require iterative and incremental fixes, also called engineering change orders (ECOs), ensuring the design integrity from an electrical and physical standpoint. All of Cadence’s signoff tools or capabilities are integrated in the Virtuoso platform, providing the same capabilities for mixed-signal and custom designs.
Knowledge and Learning
Learn about the latest Cadence offerings and solutions directly from our developers and experts. View interesting videos covering feature demos, troubleshooting information, flow launches, and more.
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.
Owner: Cadence
Product Name: Silicon Signoff and Verification (SSV)
Version: 21.10.000 (Base Release) - 21.16.000-ISR6 *
Supported Architectures: x86_64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Linux **
Size: 43.5 Gb
Base_SSV21.10.000.lnx86
Hotfix_SSV21.11.000-ISR1.lnx86
Hotfix_SSV21.12.000-ISR2.lnx86
Hotfix_SSV21.13.000-ISR3.lnx86
Hotfix_SSV21.14.000-ISR4.lnx86
Hotfix_SSV21.15.000-ISR5.lnx86
Hotfix_SSV21.16.000-ISR6.lnx86
Hotfix_SSV21.11.000-ISR1.lnx86
Hotfix_SSV21.12.000-ISR2.lnx86
Hotfix_SSV21.13.000-ISR3.lnx86
Hotfix_SSV21.14.000-ISR4.lnx86
Hotfix_SSV21.15.000-ISR5.lnx86
Hotfix_SSV21.16.000-ISR6.lnx86
Supported OS and Platform Levels
================================
This build is based on the 2021 platform support matrix, linux only. From this release onwards RH7.4 is the minimum requirement and won't run on RH6.X.
![Cadence SSV Release Version 21.16.000]()
================================
This build is based on the 2021 platform support matrix, linux only. From this release onwards RH7.4 is the minimum requirement and won't run on RH6.X.
Cadence SSV Release Version 21.16.000
Please visit my blog
Added by 3% of the overall size of the archive of information for the restoration
No mirrors please
![Cadence SSV Release Version 21.16.000]()
Added by 3% of the overall size of the archive of information for the restoration
No mirrors please
Cadence SSV Release Version 21.16.000
