Cadence SPB Allegro and OrCAD 17.40.000-2019 QIR3 (HF019)

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CCRID Product ProductLevel2 Title
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2441710 ADW PART_MANAGER Symbol version mismatch in vault and Database Editor causes symbol not loading error in System Capture when placing part
2472067 ADW PART_MANAGER Part Manager shows symbol status as not in sync when added to System Capture schematic from Pulse Unified Search
2473274 ADW TDO-SHAREPOIN Reduce number of Error and Warning messages in TDO SharePoint server
2230630 ALLEGRO_EDITOR 3D_CANVAS Some parts are missing from 3D PDF but are fine in 3D Canvas
2446115 ALLEGRO_EDITOR COLOR The Nets tab of Color dialog does not display Nets objects as default in release 17.4-2019
2280395 ALLEGRO_EDITOR CROSS_SECTION Info tab in the Cross-Section Editor does not get dynamically updated.
2295028 ALLEGRO_EDITOR CROSS_SECTION Warning not displayed for unused pad suppression in PCB Editor in release 17.4-2019
2408477 ALLEGRO_EDITOR CROSS_SECTION Cross-Section Editor Total Thickness does not update when you change any copper or dielectric thickness
2433647 ALLEGRO_EDITOR CROSS_SECTION SigXplorer crashes on editing layer stackups
2262119 ALLEGRO_EDITOR DATABASE Database check provides misleading result: Cannot find coordinate of bad segment
2440217 ALLEGRO_EDITOR DATABASE Adding via structure in design crashes PCB Editor
2496562 ALLEGRO_EDITOR DATABASE Crash in Allegro PCB Editor on quickview of design with large number of void shapes
2307662 ALLEGRO_EDITOR DFA DFA S:S spacing check does not work properly for parts rotated 45 degrees.
2399909 ALLEGRO_EDITOR DFA DFA table does not re-calculate values to BRD Database units
2141357 ALLEGRO_EDITOR DFM Cannot load custom true DFM template with wizard
2190514 ALLEGRO_EDITOR DFM False error displayed for acid trap when moving via within area.
2439697 ALLEGRO_EDITOR DFM Max line into pad ratio (SMD) is not working properly
2061941 ALLEGRO_EDITOR DRC_CONSTR Table Entry for Return Path is not returning DRC
2144596 ALLEGRO_EDITOR DRC_CONSTR Return Path DRC is not working for the table option to set up another layer to be the reference plane
2149041 ALLEGRO_EDITOR DRC_CONSTR Switching to Return Path Table in CM does not show any DRC
2226928 ALLEGRO_EDITOR DRC_CONSTR Return Path DRC does not check correctly for overlap between Anti Pad and Void.
2227126 ALLEGRO_EDITOR DRC_CONSTR Return Path DRC which is set by ECSet does not check correctly.
2252021 ALLEGRO_EDITOR DRC_CONSTR DRC marker disappears when the edge of void overlaps the center of the cline.
2431970 ALLEGRO_EDITOR DRC_CONSTR Match Via count constraints showing failed
2439508 ALLEGRO_EDITOR EDIT_ETCH Add different illumination color for pins of connections associated with differential pair
2439672 ALLEGRO_EDITOR EDIT_ETCH 'Allegro PCB Designer' license without the 'High-Speed' option results in warning 'Timing feedback is disabled'
2469702 ALLEGRO_EDITOR EDIT_ETCH Layer names with spaces cause Allegro PCB Editor to crash when running AiDT
2485514 ALLEGRO_EDITOR EDIT_ETCH Daisy chain topology: Cline width changes from constraint value when sliding
2492625 ALLEGRO_EDITOR EDIT_ETCH Timing Delays units of nano seconds (ns) in OrCAD PCB Designer Professional
2476218 ALLEGRO_EDITOR GRAPHICS Allegro Viewer crashes if disable_gpu is not set under Setup>User Preferences > Unsupported category
2423616 ALLEGRO_EDITOR INTERACTIV The copy command with 'ix' and 'iy' does not work correctly if grid is set to 5
2433310 ALLEGRO_EDITOR INTERACTIV Copy pin command results in wrong location while using ix with new position
2458671 ALLEGRO_EDITOR INTERACTIV The Via/Padstack selection option is not showing any Vias for selection when adding Via Arrays.
2480553 ALLEGRO_EDITOR INTERACTIV Padstack > Replace does not update pads immediately
2457727 ALLEGRO_EDITOR MCAD_COLLAB Display warning message for placed symbol if imported IDF EMN does not match netlist
2499455 ALLEGRO_EDITOR MODULES Placing a large module takes approximately one hour in Allegro PCB Editor
2270279 ALLEGRO_EDITOR MULTI_USER Allegro Symphony commands sent but reply to accept changes from server is not working
2463335 ALLEGRO_EDITOR ORIGIN_EEP Cross probing of pins not working from Allegro System Capture to Allegro PCB Editor
2430080 ALLEGRO_EDITOR PAD_EDITOR Cannot open some release 17.22016 padstacks in Padstack Editor in release 17.4-2019, HotFix 013
2438016 ALLEGRO_EDITOR PAD_EDITOR Trying to change the padstack of the netshort component leads to a crash of PCB Editor.
2457636 ALLEGRO_EDITOR PAD_EDITOR Pad shapes in Pad Editor - width and height should not be editable
2472971 ALLEGRO_EDITOR PAD_EDITOR Cannot open some release 17.2-2016 padstacks in release 17.4-2019
2480047 ALLEGRO_EDITOR PAD_EDITOR Get Error Message SPMHA1-161 when trying to open Padstack from directory containing accented word
2472407 ALLEGRO_EDITOR PLACEMENT Not possible to create via array using vias with long names
2187696 ALLEGRO_EDITOR SHAPE Shape with Fill style 'Xhatch' causes stray copper segments shorting with Thru via
2354027 ALLEGRO_EDITOR SHAPE The NO_SHAPE_CONNECT property is not respected for two instances in the designs
2434357 ALLEGRO_EDITOR SHAPE Islands keep on returning when shapes are updated
2441674 ALLEGRO_EDITOR SHAPE 'Automatically delete antenna shapes' does not work correctly for full contact thermal
2489160 ALLEGRO_EDITOR SHAPE "Auto delete isolated / antenna shapes" removes connected GND shape unexpectedly
2455424 ALLEGRO_EDITOR UI_FORMS axlFormSetField() does not accept special characters correctly.
2412868 ALLEGRO_EDITOR UI_GENERAL axlMeterUpdate() does not seem to work as expected if used inside a SKILL function in a .il file
2416898 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016 and 17.4-2019 issue with axlFormGridSetSelectRows: Cannot deselect first selected row
2425502 ALLEGRO_EDITOR UI_GENERAL Alias or funckey for SF10 is not working
2434387 ALLEGRO_EDITOR UI_GENERAL Shift F10 does not work "alias SF10 clpCopy" in release 17.4-2019 but works in release 17.2-2016
2439140 ALLEGRO_EDITOR UI_GENERAL Issue with toolbar items disappearing on next invocation
2441723 ALLEGRO_EDITOR UI_GENERAL Shift+F7 does not dehighlight all nets
2333383 APD 3D_CANVAS Soldermask not transferred to 3D Canvas
2434323 APD 3D_CANVAS Soldermask layer not transferred to 3D Canvas
2499713 APD DATABASE APD Metal Usage Report shows failed layer in release 17.4-2019
2464988 APD DEGASSING Advanced degassing adding voids on overlapping shapes in same layer is wrong
2423797 APD DRC_CONSTRAIN 'add fillet' command ignores Route_keepout.
2439680 APD DRC_CONSTRAIN Void Sliver check is not throwing the DRC
2449611 APD DRC_CONSTRAIN Keepout to Fillet Error: No DRCs reported for fillet
2483992 APD EXTRACT axlExtractToFile with crosshatch option generates incorrect circle randomly.
2361524 CAPTURE PROJECT_MANAG Find results window shows no contents for Variant Parts, although Session.log results in matches
2399955 CM OTHER Release 17.4-2019 executables marked or removed by anti-virus software
2455058 CM OTHER Sigcheck does not find Digital signatures for Installation EXEs
2445118 CONCEPT_HDL CONSTRAINT_MG Auto Generate - All generates Signal Models for components that have models
2472838 CONCEPT_HDL CORE ERROR(SPCOCN-3420) while opening a newly created Project.
2477330 CONCEPT_HDL CORE Unable to package the design. Pxl.exe stops working.
2481432 CONCEPT_HDL CORE DE-HDL performance issue - Slowdown on large hierarchical designs with netgroups
2484869 CONCEPT_HDL HDLDIRECT Genview fails to update symbol
2513868 CONCEPT_HDL HDLDIRECT Net Group(Schematic) limitation in Concept HDL
2411504 CONCEPT_HDL OTHER Split symbol port distribution information is lost when directory structure contains a dash (-) character
2477665 CONCEPT_HDL OTHER DE-HDL background color change does not take effect until tool is relaunched
2482736 CONSTRAINT_MGR DATABASE Crash when opening a SiP design in release 17.2-2016 saved in release 17.4-2019
2282855 CONSTRAINT_MGR INTERACTIV Message about busy host application appears when editing any field in CM
2358338 CONSTRAINT_MGR INTERACTIV Constraint Manager cannot export DRC worksheet file and displays incorrect error (SPCMGR-300)
2279678 CONSTRAINT_MGR OTHER Export HTML report from CM does cannot save Net Class-Class/CSet assignment matrix report
2417609 CONSTRAINT_MGR OTHER Script does not terminate if CM > View Options > Restore Default Setting is part of the recorded step
2187880 CONSTRAINT_MGR UI_FORMS Enabling the option "Exact Match" within the "Find and Replace" UI does not find the object
2307492 CONSTRAINT_MGR UI_FORMS CM double scroll bar on resize UI
2422624 CONSTRAINT_MGR UI_FORMS ViaList Filter: Search is difficult because wild characters are not supported
2467437 CONSTRAINT_MGR UI_FORMS Allegro Constraint Manager stub length values are not reported for a board although check is turned on
2152823 INSTALLATION DOWNLOAD_MGR Download Manager should delete previous hotfixes
2409941 INSTALLATION DOWNLOAD_MGR Download Manager Cache cleanup option to delete previous updates
2424691 ORBITIO LEFDEFINTERFA BLOCKAGES do not shrink during DEF import.
2430493 ORBITIO OTHER OrbitIO: Some net connections were lost during DEF/Verilog export.
2487964 PCB PARTDEF In all SPB frontend products, including DE-HDL, Board data does not get opened with "Launch PCB Viewer"
2503271 PCB PARTDEF PCB Viewer opens in wrong directory when viewing board from Capture
2504842 PCB PARTDEF Cannot start PSpice due to system PolyBool.dll not found error
2233715 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor does not respond when Metrics unit is used in PDV Symbol setup.
2338020 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor stops responding on selecting Metric in Part Developer
2496631 PCB_LIBRARIAN SYMBOL_EDITOR Allegro System Capture crashes when adding parts created using the Save As command in Part Developer
2427183 PCB_LIBRARIAN SYM_CREATOR_U Text justification not enabled in the Property view in new Symbol Editor
2472172 PSPICE ENVIRONMENT Specification of PSpice Basic: Measurement not available
2429506 PULSE CORE Trim PULSE_REMOTE_URL variable
2432729 PULSE CORE Linux service status init.d script has string from pre-QIR1
2464561 PULSE CORE In System Capture placing a component takes a long time
2466539 PULSE CORE License is not checked out while running 'vista -test true'
2455934 PULSE UNIFIED_SEARC System Capture allows placement of EOL/Obsolete parts on schematic
2478315 PULSE UNIFIED_SEARC Placing yellow/red life cycle parts using the ' + ' in the Part Details panel is allowed
2438014 PULSE WORKFLOWS Pulse master node starting in maintenance mode with 'Pulse Workflow service could not be started due to internal error.'
2439787 PULSE WORKFLOWS Pulse Master Server - Maintenance Mode - The "Pulse Workflow" service could not be started due to internal error.
2455153 PULSE WORKFLOWS Error (SPDWSRV-515) when trying to save workflow changes: Unable to publish workflow due to an internal error
2011623 SIP_LAYOUT CROSS_SECTION Differences in .sip files on updating to newer release after performing front-to-back and back-to-front flow
2288593 SIP_LAYOUT SHAPE Auto voiding of dynamic shape does not keep enough space between via and surrounding dynamic shape
2484688 SPEED2000 ENG_SPDSIM TopXP extraction workflow does not recognize differential pairs
2421973 SYSTEM_CAPTURE ADD_COMPONENT Section information defined in the library is lost in System Capture on the placed instances
2442936 SYSTEM_CAPTURE CONSTRAINT_MA Directive EDIT_PHYSICAL_SPACING_CONSTRAINTS is getting added to the project CPM file
2462955 SYSTEM_CAPTURE COPY_PROJECT System Capture 'Copy As' does not work correctly when you are using same project or design name
2465391 SYSTEM_CAPTURE COPY_PROJECT CopyProject fails to copy the sdax file from the source design to the destination design
2352578 SYSTEM_CAPTURE DARK_THEME Strange behavior with text colors. When switching to Dark theme, the white text remains black
2415444 SYSTEM_CAPTURE DOCKED_CM Constraint Manager Update to System Capture not working
1993646 SYSTEM_CAPTURE DRC False Property overlap DRCs reported. Cross-probing not working on decap groups
2108856 SYSTEM_CAPTURE DRC Overlapping text DRC not checking the actual text but the oversized bounding box
2486774 SYSTEM_CAPTURE DRC Single Node Net DRC should not report an error for nets connected between a pin and power symbol or port symbol.
2428876 SYSTEM_CAPTURE EXPORT_PCB Dismissing the Export Physical success pop-up does not revert control to the application - there's a delay
2135397 SYSTEM_CAPTURE GRID Modified Symbol does not get updated using Part Manager
2461165 SYSTEM_CAPTURE IMPORT_BLOCK Match Group members are different as compared what they are in DE-HDL
2344526 SYSTEM_CAPTURE IMPORT_DEHDL_ DE-HDL design with hyphen in name cannot be read using File - New - Project from existing design
2346688 SYSTEM_CAPTURE IMPORT_DEHDL_ Getting 'Pin cannot be packaged' error
2350812 SYSTEM_CAPTURE IMPORT_DEHDL_ Ground connection broken after importing DE-HDL design to System Capture.
2467395 SYSTEM_CAPTURE IMPORT_DEHDL_ Attempting to import a hierarchical DE-HDL design into System Capture fails
2469775 SYSTEM_CAPTURE IMPORT_DEHDL_ Ability to support dashes in project names, design names, and block names
2291400 SYSTEM_CAPTURE INSERT_PICTUR Right-click - delete image does not work after changing picture transparency
2423432 SYSTEM_CAPTURE MENUS_AND_TOO 'addSeparator' does not load from Tcl script
2307495 SYSTEM_CAPTURE MISCELLANEOUS Bundle arrowhead changes direction when doing an undo
2187909 SYSTEM_CAPTURE NETGROUP After adding a signal to a lower level NetGroup, that member net should be available at the top level
2276987 SYSTEM_CAPTURE NETGROUP NetGroups renaming signals in Allegro System Capture
2362869 SYSTEM_CAPTURE NETGROUP Allegro System Capture cannot incrementally add sub-NetGroups to an existing NetGroup
2364377 SYSTEM_CAPTURE NETGROUP System Capture renames NetGroup members when they already exist in the design
2415751 SYSTEM_CAPTURE NETGROUP Allegro System Capture shows 7 members in NetGroup while Constraints tab and CM show 8 members
2440091 SYSTEM_CAPTURE NETGROUP Netgroup Selection Stops Working
2490739 SYSTEM_CAPTURE PACKAGER Packaging error 1130 and 10002 while using two different blocks which stops the netlist generation at top
2280515 SYSTEM_CAPTURE PART_MANAGER Prevent invalid properties being added to Allegro System Capture with ANNOTATE_ALL_PROPS directive
2444662 SYSTEM_CAPTURE PART_MANAGER Symbol does not get updated on schematic and continues to show not in sync
2047543 SYSTEM_CAPTURE PRINT Print preview should work the same way as in DE-HDL
2340783 SYSTEM_CAPTURE PRINT Print destination setting does not remember previous selection.
2465043 SYSTEM_CAPTURE PRINT 'Current Page' option in the Print settings does not work.
2428835 SYSTEM_CAPTURE REPLACE Design corruption after Allegro System Capture crashing
2446037 SYSTEM_CAPTURE REPLACE Allegro System Capture - HDL_POWER property disappeared for many power symbols on the design after uprev
2483574 SYSTEM_CAPTURE REPLACE Power component does not retain power name on copy
2428902 SYSTEM_CAPTURE SCRIPTING System Capture getDesignEnvironment API returns DE-HDL
2418108 SYSTEM_CAPTURE SHORTCUTS Keyboard shortcuts are not working
2500644 SYSTEM_CAPTURE SHORTCUTS System Capture saves user shortcuts in the wrong location
2292556 SYSTEM_CAPTURE SMART_PDF SmartPDF of images inserted on canvas pages are very blurry
2325580 SYSTEM_CAPTURE SMART_PDF Smart PDF colors do not match schematic
2458513 SYSTEM_CAPTURE SMART_PDF Signal names rotated 90 degree are getting printed in a larger font
2205370 SYSTEM_CAPTURE SPECIAL SYMBO Can only add one Special Symbol for the Alias group
2360529 SYSTEM_CAPTURE SPECIAL SYMBO Cannot have multiple bodies in the alias body special symbol
2291733 SYSTEM_CAPTURE UI Unable to delete selected objects with Del key or the Edit->Delete after adjusting Selection Filter.
2408448 SYSTEM_CAPTURE UI Undocked pane behind other undocked panes does not come into focus when it should
2018797 SYSTEM_CAPTURE VARIANT_MANAG The Variant Editor spreadsheet fails to de-highlight cells from canvas cross-probe
2155354 SYSTEM_CAPTURE VARIANT_MANAG Font, Line and Color not as per settings in Variant Schematic
2354623 SYSTEM_CAPTURE VARIANT_MANAG Variant view settings for alternate parts does not apply dynamically
2447803 SYSTEM_CAPTURE VARIANT_MANAG When importing design from DE-HDL to System Capture, the variant data for alternative components is not visible
2462766 SYSTEM_CAPTURE VARIANT_MANAG Problem with variants when migrating a design from DE-HDL to Allegro System Capture
2206618 SYSTEM_CAPTURE WIRING OK button not active after paste in a table of new bit numbers in the Change Bit Number GUI
2439053 SYSTEM_CAPTURE WIRING System Capture does not respond on using the command 'drawWire' in the console window
2463284 SYSTEM_CAPTURE WIRING Wire on Pgnd symbol has been deleted but signal net exists
2504498 SYSTEM_DESIGN SDE_EXPORT_SU 'Export SubSystems Project' reports failure although log file indicates success
2486837 TOPXP ALLEGRO_INTEG All bi-directional pins are incorrectly recognized as Rx
2442721 TOPXP SYSTEMSI Simulation is aborted when a 776 MB model is loaded
2470058 TOPXP SYSTEMSI PRBS generates all 111* patterns when 127 bits are set with poly 7
2424750 TOPXP TOPXPLORER Unable to switch Transmit IO models for diff pair in Topology Explorer, but able to switch in System Explorer
2460615 TOPXP TOPXPLORER Extracting a net from Aurora to Topology Explorer takes a long time compared to SigXplorer (less than a minute).
2506025 TOPXP TOPXPLORER Incorrect Topology Explorer simulation results for differential signal

System Requirements:

OS: Windows 10 (64-bit) Professional, Windows Server 2012 (All Service Packs); Windows Server 2012 R2; Windows Server 2016.
CPU: Intel Core i7 4.30 GHz or AMD Ryzen 7 4.30 GHz with at least 4 cores
Memory: 16 GB RAM
Space: 50 GB free disk space (SSD drive is recommended)
Display: 1920 x 1200 display resolution with true color (at least 32bit color)
GPU: A dedicated graphics card supporting OpenGL, minimum 2GB (with additional support for DX11 for 3D Canvas)
Monitors: Dual monitors (For physical design)
Supported MATLAB Version: R2019A-64Bit (For the PSpice-MATLAB interface)