Cadence Allegro and OrCAD 17.20.000-2016 HF031
Cadence Allegro and OrCAD 17.20.000-2016 HF031 | 2.5 Gb
Cadence Design Systems, Inc. has released an update (HF031) to OrCAD Capture, PSpice Designer and PCB Designer 17.20.000-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
1746108 ADW DBADMIN Adding and then saving a custom rule set in rule manager results in corrupt rules.xml
1609983 ADW DBEDITOR dbeditor should automatically change mechanical kit names to uppercase
1807139 ADW DBEDITOR Cannot add new properties, though the new properties were shown in dbeditor
1807410 ADW LIB_FLOW Checked-in parts not available in database
1797408 ADW TDA TDO crashes without displaying exception during check-in
1804500 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas fails to show all placebounds of a .dra
1810758 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer represents symbol incorrectly in hotfix 025 but as expected in hotfix 024
1795567 ALLEGRO_EDITOR EDIT_ETCH Route menu has same hot key for 'Connect' and 'Convert Fanout'
1796525 ALLEGRO_EDITOR EDIT_ETCH AiPT is not pushing dynamic shape to add bumps to resolve dynamic phase DRC
1818170 ALLEGRO_EDITOR EDIT_ETCH Fanout with Outward Via direction is shorting few pins
1712658 ALLEGRO_EDITOR INTERACTIV Add connect: Pin remains highlighted even after choosing 'Done'
1727193 ALLEGRO_EDITOR INTERACTIV Logic - Part List truncates device names to 64 characters though database allows longer names
1775484 ALLEGRO_EDITOR INTERACTIV Choosing Next with persistent snap in Show Measure disables persistent snap
1711860 ALLEGRO_EDITOR MULTI_USER Multi-user lock cannot be cancelled
1812448 ALLEGRO_EDITOR NC Crash when canceling NC Parameters dialog
1792987 ALLEGRO_EDITOR PAD_EDITOR Pad Designer does not recognize flash names longer than 31 characters
1810958 ALLEGRO_EDITOR PAD_EDITOR Padstacks with offset holes
787024 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
793232 ALLEGRO_EDITOR SHAPE Line to Shape spacing rule outside region affects shape void in region
797245 ALLEGRO_EDITOR SHAPE Line to Shape Spacing with Region not followed
865822 ALLEGRO_EDITOR SHAPE The autovoid functionality should use the true line-to-shape spacing value
912051 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
965714 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly on dynamic shapes
968342 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region is taking conservative value and not the actual spacing value
974734 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
1073908 ALLEGRO_EDITOR SHAPE Allow line to shape spacing in Region
1154787 ALLEGRO_EDITOR SHAPE Region constraints not applied correctly to dynamic shapes
1171283 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
1181767 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
1183792 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
1186210 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region value
1192312 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly.
1387021 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in Regions
1447891 ALLEGRO_EDITOR SHAPE Resolved constraint and actual air gap differ
1465383 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region
1583144 ALLEGRO_EDITOR SHAPE Line to shape spacing inside the constraint region does not follow region rules
1591320 ALLEGRO_EDITOR SHAPE Resolve shape to pin constraint in constraint region
1627305 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
1694552 ALLEGRO_EDITOR SHAPE Constraint region not working correctly
1764474 ALLEGRO_EDITOR SHAPE Line to Shape Spacing for Region should be used inside region instead of conservative value
1775119 ALLEGRO_EDITOR SHAPE Shape voiding is not following constraint rules for dynamic shapes in a constraint region
1784916 ALLEGRO_EDITOR SHAPE Shapes are not voiding to other shapes against DRC settings, creating random DRCs.
1793179 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
1803365 ALLEGRO_EDITOR SHAPE Region shape to shape constraints take precedence when shapes have multiple constraints
1800530 ALLEGRO_EDITOR UI_FORMS 3D Anchor menu missing when using new style OrCAD PCB Editor menu
1813604 ALLEGRO_EDITOR UI_FORMS 3D Anchor View is not available on OrCAD PCB Editor menu.
1784710 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
1784728 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
1721853 ASDA CANVAS_EDIT Movement of components results in shorts and inconsistent routing
1802120 ASDA CONTEXT_MENUS Ports are selected though filter is set to Components
1803832 ASDA MISCELLANEOUS Browse and select new libraries without editing cds.lib
1804643 ASDA TABLE Exception when pasting table data from third-party tool in SDA
1794004 CAPTURE LIBRARY Diode pin numbers different in Capture in release 16.6 and 17.2-2016
1735506 CAPTURE OTHER File menu is missing in Capture
1766663 CAPTURE SCHEMATICS Capture crashes during part placement
1762181 CAPTURE SCHEMATIC_EDI Crash on 'Push Occ. Prop into Instance'
1786762 CAPTURE SCHEMATIC_EDI 'Remove Occurrence Properties' and 'Push Occ. Prop into Instance' corrupt database
1759424 CIS PART_MANAGER Unable to save the link database part from part manager
1802670 CONCEPT_HDL CORE Variant commands take 6 to 10 hours to run on a block
1816798 CONSTRAINT_MGR CONCEPT_HDL CM API ACNS_DESIGN returns the design name in mixed case
1812656 CONSTRAINT_MGR DATABASE Constraint Value specified at the DEFAULT PCSet/SCSet is not shown in bold blue
1635766 CONSTRAINT_MGR UI_FORMS Worksheet views are not changed as per input
1700505 ECW PART_LIST_MAN Shopping Cart Quantity is not read or not displayed in Pulse
1797371 ECW PROJECT_MANAG Clicking on another project sometimes takes you to the default project instead of the project you click on
1843526 INSTALLATION TRIAL Trial installer should not check disk space in update licensing mode
1762148 PCB_LIBRARIAN SETUP Part Developer: Text not readable in Setup form
1770760 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor does not remember the last size of the window
1773604 PCB_LIBRARIAN SYMBOL_EDITOR Option to switch between the new and legacy Symbol Editors
1800354 PCB_LIBRARIAN SYMBOL_EDITOR Resistor has too many lines and looks wrong in new symbol editor
1813346 PCB_LIBRARIAN SYMBOL_EDITOR Resistor looks different with multiple diagonal lines in new Symbol Editor but looks normal in DE-HDL
1815279 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings from Lines to Dots
1738603 PSPICE DIG_SIMULATOR Release 17.2-2016 PSpice digital model: Delay defined by PINDLY is not taken into account
1802905 PSPICE ENCRYPTION Incorrect option shown in PSpiceENC syntax in usage detail
1765345 PSPICE ENVIRONMENT Custom distributions are not added to the dropdown
1784856 PSPICE ENVIRONMENT PSpice ignoring directory changes for Save check point in simulation setup session
1817805 PSPICE ENVIRONMENT Incorrect result for PSpice 'Start saving data after'
1784507 PSPICE FRONTENDPLUGI Spelling of 'Definition' in PSpice Part Search is not correct
1801790 PSPICE LIBRARIES SAC model giving errors
1738776 PSPICE SIMULATOR PSpice simulation stops before TSTOP
1795950 PSPICE SIMULATOR Simulation cannot be completed in release 17.2-2016 but is completed in release 16.6
1803407 PSPICE SIMULATOR Getting convergence error on a model
1814759 PSPICE SLPS .INC file is not working with SLPS
1715859 SIP_LAYOUT ETCH_BACK Etchback mask not overlapping each other; creating floating metal
1729523 SIP_LAYOUT INTERACTIVE When creating a bond finger solder mask the results do not match the required settings
1800069 SIP_LAYOUT INTERACTIVE Corrupt dra/psm symbol, but the reason is unclear
1756620 SIP_LAYOUT SHAPE Performance issue when moving vias.
1782928 SIP_LAYOUT SHAPE Shape merging (logical operation) shows error though measuring shows elements are correctly spaced
1816454 SIP_LAYOUT THIEVING Thieving: need thieving as a specific data type in CM to better control the filling pattern
1728026 TDA CORE Check-in should not require all child objects to be checked in specially if they are not checked-out
1823976 TDA SHAREPOINT Connection to server terminates when joining a project
1609983 ADW DBEDITOR dbeditor should automatically change mechanical kit names to uppercase
1807139 ADW DBEDITOR Cannot add new properties, though the new properties were shown in dbeditor
1807410 ADW LIB_FLOW Checked-in parts not available in database
1797408 ADW TDA TDO crashes without displaying exception during check-in
1804500 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas fails to show all placebounds of a .dra
1810758 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer represents symbol incorrectly in hotfix 025 but as expected in hotfix 024
1795567 ALLEGRO_EDITOR EDIT_ETCH Route menu has same hot key for 'Connect' and 'Convert Fanout'
1796525 ALLEGRO_EDITOR EDIT_ETCH AiPT is not pushing dynamic shape to add bumps to resolve dynamic phase DRC
1818170 ALLEGRO_EDITOR EDIT_ETCH Fanout with Outward Via direction is shorting few pins
1712658 ALLEGRO_EDITOR INTERACTIV Add connect: Pin remains highlighted even after choosing 'Done'
1727193 ALLEGRO_EDITOR INTERACTIV Logic - Part List truncates device names to 64 characters though database allows longer names
1775484 ALLEGRO_EDITOR INTERACTIV Choosing Next with persistent snap in Show Measure disables persistent snap
1711860 ALLEGRO_EDITOR MULTI_USER Multi-user lock cannot be cancelled
1812448 ALLEGRO_EDITOR NC Crash when canceling NC Parameters dialog
1792987 ALLEGRO_EDITOR PAD_EDITOR Pad Designer does not recognize flash names longer than 31 characters
1810958 ALLEGRO_EDITOR PAD_EDITOR Padstacks with offset holes
787024 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
793232 ALLEGRO_EDITOR SHAPE Line to Shape spacing rule outside region affects shape void in region
797245 ALLEGRO_EDITOR SHAPE Line to Shape Spacing with Region not followed
865822 ALLEGRO_EDITOR SHAPE The autovoid functionality should use the true line-to-shape spacing value
912051 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
965714 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly on dynamic shapes
968342 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region is taking conservative value and not the actual spacing value
974734 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
1073908 ALLEGRO_EDITOR SHAPE Allow line to shape spacing in Region
1154787 ALLEGRO_EDITOR SHAPE Region constraints not applied correctly to dynamic shapes
1171283 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
1181767 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
1183792 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
1186210 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region value
1192312 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly.
1387021 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in Regions
1447891 ALLEGRO_EDITOR SHAPE Resolved constraint and actual air gap differ
1465383 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region
1583144 ALLEGRO_EDITOR SHAPE Line to shape spacing inside the constraint region does not follow region rules
1591320 ALLEGRO_EDITOR SHAPE Resolve shape to pin constraint in constraint region
1627305 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
1694552 ALLEGRO_EDITOR SHAPE Constraint region not working correctly
1764474 ALLEGRO_EDITOR SHAPE Line to Shape Spacing for Region should be used inside region instead of conservative value
1775119 ALLEGRO_EDITOR SHAPE Shape voiding is not following constraint rules for dynamic shapes in a constraint region
1784916 ALLEGRO_EDITOR SHAPE Shapes are not voiding to other shapes against DRC settings, creating random DRCs.
1793179 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
1803365 ALLEGRO_EDITOR SHAPE Region shape to shape constraints take precedence when shapes have multiple constraints
1800530 ALLEGRO_EDITOR UI_FORMS 3D Anchor menu missing when using new style OrCAD PCB Editor menu
1813604 ALLEGRO_EDITOR UI_FORMS 3D Anchor View is not available on OrCAD PCB Editor menu.
1784710 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
1784728 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
1721853 ASDA CANVAS_EDIT Movement of components results in shorts and inconsistent routing
1802120 ASDA CONTEXT_MENUS Ports are selected though filter is set to Components
1803832 ASDA MISCELLANEOUS Browse and select new libraries without editing cds.lib
1804643 ASDA TABLE Exception when pasting table data from third-party tool in SDA
1794004 CAPTURE LIBRARY Diode pin numbers different in Capture in release 16.6 and 17.2-2016
1735506 CAPTURE OTHER File menu is missing in Capture
1766663 CAPTURE SCHEMATICS Capture crashes during part placement
1762181 CAPTURE SCHEMATIC_EDI Crash on 'Push Occ. Prop into Instance'
1786762 CAPTURE SCHEMATIC_EDI 'Remove Occurrence Properties' and 'Push Occ. Prop into Instance' corrupt database
1759424 CIS PART_MANAGER Unable to save the link database part from part manager
1802670 CONCEPT_HDL CORE Variant commands take 6 to 10 hours to run on a block
1816798 CONSTRAINT_MGR CONCEPT_HDL CM API ACNS_DESIGN returns the design name in mixed case
1812656 CONSTRAINT_MGR DATABASE Constraint Value specified at the DEFAULT PCSet/SCSet is not shown in bold blue
1635766 CONSTRAINT_MGR UI_FORMS Worksheet views are not changed as per input
1700505 ECW PART_LIST_MAN Shopping Cart Quantity is not read or not displayed in Pulse
1797371 ECW PROJECT_MANAG Clicking on another project sometimes takes you to the default project instead of the project you click on
1843526 INSTALLATION TRIAL Trial installer should not check disk space in update licensing mode
1762148 PCB_LIBRARIAN SETUP Part Developer: Text not readable in Setup form
1770760 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor does not remember the last size of the window
1773604 PCB_LIBRARIAN SYMBOL_EDITOR Option to switch between the new and legacy Symbol Editors
1800354 PCB_LIBRARIAN SYMBOL_EDITOR Resistor has too many lines and looks wrong in new symbol editor
1813346 PCB_LIBRARIAN SYMBOL_EDITOR Resistor looks different with multiple diagonal lines in new Symbol Editor but looks normal in DE-HDL
1815279 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings from Lines to Dots
1738603 PSPICE DIG_SIMULATOR Release 17.2-2016 PSpice digital model: Delay defined by PINDLY is not taken into account
1802905 PSPICE ENCRYPTION Incorrect option shown in PSpiceENC syntax in usage detail
1765345 PSPICE ENVIRONMENT Custom distributions are not added to the dropdown
1784856 PSPICE ENVIRONMENT PSpice ignoring directory changes for Save check point in simulation setup session
1817805 PSPICE ENVIRONMENT Incorrect result for PSpice 'Start saving data after'
1784507 PSPICE FRONTENDPLUGI Spelling of 'Definition' in PSpice Part Search is not correct
1801790 PSPICE LIBRARIES SAC model giving errors
1738776 PSPICE SIMULATOR PSpice simulation stops before TSTOP
1795950 PSPICE SIMULATOR Simulation cannot be completed in release 17.2-2016 but is completed in release 16.6
1803407 PSPICE SIMULATOR Getting convergence error on a model
1814759 PSPICE SLPS .INC file is not working with SLPS
1715859 SIP_LAYOUT ETCH_BACK Etchback mask not overlapping each other; creating floating metal
1729523 SIP_LAYOUT INTERACTIVE When creating a bond finger solder mask the results do not match the required settings
1800069 SIP_LAYOUT INTERACTIVE Corrupt dra/psm symbol, but the reason is unclear
1756620 SIP_LAYOUT SHAPE Performance issue when moving vias.
1782928 SIP_LAYOUT SHAPE Shape merging (logical operation) shows error though measuring shows elements are correctly spaced
1816454 SIP_LAYOUT THIEVING Thieving: need thieving as a specific data type in CM to better control the filling pattern
1728026 TDA CORE Check-in should not require all child objects to be checked in specially if they are not checked-out
1823976 TDA SHAREPOINT Connection to server terminates when joining a project
About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors’ productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
- Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.
Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located here
About Hot-Fix. A Hot-Fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack. Unlike Service Packs (SP), which are scheduled, periodic releases, Hot-Fix releases are not periodically scheduled. Simply requesting a Hot-Fix does not automatically guarantee that the customer will receive it: all Hot-Fix requests first must be approved and accepted by Cadence prior to delivery. Furthermore, a Hot-Fix may contain fixes related to problems reported earlier by different customers. All the files included in the Hot-Fix will nevertheless be installed.
About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF031
Supported Architectures: x64
Website Home Page : www.cadence.com
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Size: 2.5 Gb
Cadence Allegro and OrCAD 17.20.000-2016
Please visit my blog
Added by 3% of the overall size of the archive of information for the restoration
No mirrors please
![Cadence Allegro and OrCAD 17.20.000-2016 HF031]()
Please visit my blog
Added by 3% of the overall size of the archive of information for the restoration
No mirrors please
Cadence Allegro and OrCAD 17.20.000-2016 HF031
