Risc-V Interrupts & Platform Level Interrupt Controller

Write RISC-V assembly code to configure GPIO, PLIC and Core CSRs to generate GPIO interrupt and blink blue LED on board

What you'll learn

Understand privilege levels, traps and control and status registers

Platform Level Interrupt Controller Specification

Sample implementation of PLIC module on FE310 SoC

Writing assembly code, compiling, linking with GNU tools and debugging with OpenOCD and GDB

Demonstration of interrupt generation & handling in RISC-V assembly

Requirements

Brief knowledge on any processor like interrupts, interrupt priority & interrupt handling would help

Description

Interrupts in RISC-V are governed by standards and specification. Each RISC-V core's interrupt generation and handling process should be compliant to the specification. This course discusses the following:a. Privilege Levels in RISC-Vb. Traps in RISC-Vc. Platform Level Interrupt Controller (PLIC) Specificationd. Compares PLIC Implementation on FE310 SoC to Spece. Control and Status Registers (CSRs) f. Instructions to read and write CSRs in RISC-Vg. Configuring GPIO peripheral in FE310 SoCh. Configuring PLIC to allow GPIO interrupti. Configure MIE & MSTATUS CSRs on the core  to enable machine mode interrupts and machine mode external interruptsj. Installation of GNU tools (compilers, OpenOCD)k. Test application in assembly to blink blue LED on Hifive1-Rev B board.Students who enrol would be taken through a journey starting from basics of what are interrupts, exceptions and traps in RISC-V, followed by PLIC standard discussing the parameters, how to configure those parameters on PLIC to generate interrupt and claiming and completing the interrupt handling process and finally on writing an test application to blink LED. The major exercise and focus on this course is on writing RISC-V assembly code, assembling & linking with GNU tools, generating ELF, and programming it on Hifive1-RevB board to blink blue LED on board.

Overview

Section 1: Introduction

Lecture 1 Course Overview

Section 2: Privilege Levels and Traps in RISC-V

Lecture 2 Privilege Levels in RISC-V

Lecture 3 Traps in RISC-V

Section 3: Platform Level Interrupt Controller Specification

Lecture 4 Need for PLIC Specification

Lecture 5 Interrupt Flow in PLIC

Lecture 6 Operational Block Diagram

Lecture 7 PLIC Parameters Memory Map In FE310 SoC

Section 4: Install tools, write simple assembly code, compile, link and generate ELF

Lecture 8 Install OpenOCD and GNU Toolchain

Lecture 9 Demo Compile, Load, Execute and Debug with OpenOCD and GDB

Section 5: Section 5: Control and Status Registers

Lecture 10 Introduction to & demonstration of accessing Control and Status Registers

Section 6: Hands on with Hifive1-Rev Board

Lecture 11 Introduction

Lecture 12 Configure GPIO 21

Lecture 13 Configure PLIC to allow GPIO 21 interrupt

Lecture 14 Configure E31 core CSRs to enable machine and machine external interrupt

Lecture 15 Test application to blink the blue LED and generate interrupt

Embedded system developers and RISC-V enthusiasts