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Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes (Repost)

Posted By: step778
Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes (Repost)

Ban P. Wong, Anurag Mittal, Greg W. Starr, "Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes"
2008 | pages: 394 | ISBN: 0470112808 | PDF | 13,0 mb

Discover innovative tools that pave the way from circuit andphysical design to fabrication processing
Nano-CMOS Design for Manufacturability examines the challengesthat design engineers face in the nano-scaled era, such asexacerbated effects and the proven design for manufacturability(DFM) methodology in the midst of increasing variability and designprocess interactions. In addition to discussing the difficultiesbrought on by the continued dimensional scaling in conformance withMoore's law, the authors also tackle complex issues in the designprocess to overcome the difficulties, including the use of afunctional first silicon to support a predictable product ramp.Moreover, they introduce several emerging concepts, includingstress proximity effects, contour-based extraction, and designprocess interactions.
This book is the sequel to Nano-CMOS Circuit and PhysicalDesign, taking design to technology nodes beyond 65nm geometries.It is divided into three parts:
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Part One, Newly Exacerbated Effects, introduces the newlyexacerbated effects that require designers' attention, beginningwith a discussion of the lithography aspects of DFM, followed bythe impact of layout on transistor performance
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Part Two, Design Solutions, examines how to mitigate the impactof process effects, discussing the methodology needed to makesub-wavelength patterning technology work in manufacturing, as wellas design solutions to deal with signal, power integrity, WELL,stress proximity effects, and process variability
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Part Three, The Road to DFM, describes new tools needed tosupport DFM efforts, including an auto-correction tool capable offixing the layout of cells with multiple optimization goals,followed by a look ahead into the future of DFM
Throughout the book, real-world examples simplify complexconcepts, helping readers see how they can successfully handleprojects on Nano-CMOS nodes. It provides a bridge that allowsengineers to go from physical and circuit design to fabricationprocessing and, in short, make designs that are not onlyfunctional, but that also meet power and performance goals withinthe design schedule.

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